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ICS8S89831I Datasheet

Differential LVPECL-To-LVPECL/ECL Fanout Buffer

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ICS8S89831I pdf
Differential LVPECL-To-LVPECL/ECL
Fanout Buffer
ICS8S89831I
DATA SHEET
General Description
The ICS8S89831I is a high speed 1-to-4 Differential-
ICS to-LVPECL/ECL Fanout Buffer. The ICS8S89831I is
HiPerClockS™ optimized for high speed and very low output skew,
making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet,
and Fibre Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as LVDS,
LVHSTL and CML to be easily interfaced to the input with minimal
use of external components. The device also has an output enable
pin which may be useful for system test and debug purposes. The
ICS8S89831I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
Four LVPECL/ECL outputs
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
50internal input termination to VT
Output frequency: >2.1GHz
Output skew: 30ps (maximum)
Part-to-part skew: 185ps (maximum)
Additive phase jitter, RMS: 0.31ps (typical)
Propagation Delay: 570ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.5V±5%, 3.3V±5%, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.3V±5%, -2.5V±5%
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
EN Pullup
DQ
IN
VT 50
nIN 50
VREF_AC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
10 VREF_AC
nQ2 4
9 nIN
5 6 78
ICS8S89831I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89831AKI REVISION A APRIL 26, 2010
1
©2010 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS8S89831I Datasheet

Differential LVPECL-To-LVPECL/ECL Fanout Buffer

No Preview Available !

ICS8S89831I pdf
ICS8S89831I Data Sheet
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
7, 14
8
9
10
11
12
13
15, 16
Vcc
EN
nIN
VREF_AC
VT
IN
VEE
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Power supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN input. Input threshold is VCC/2. Includes a
37kpull-up resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications.
Termination input. IREF_AC (max.) < ±2mA.
Non-inverting LVPECL differential clock input.
RT = 50termination to VT.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
ICS8S89831AKI REVISION A APRIL 26, 2010
2
©2010 Integrated Device Technology, Inc.


Part Number ICS8S89831I
Description Differential LVPECL-To-LVPECL/ECL Fanout Buffer
Maker IDT
Total Page 21 Pages
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