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Integrated Device Technology Electronic Components Datasheet

ICS8735I-21 Datasheet

ZERO DELAY CLOCK GENERATOR

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ICS8735I-21 pdf
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8735I-21 is a highly versatile 1:1 Differential-to-
3.3V LVPECL clock generator. The CLK, nCLK pair can
accept most standard differential input levels. The
ICS8735I-21 has a fully integrated PLL and can be config-
ured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The ref-
erence divider, feedback divider and output divider
are each programmable, thereby allowing for the following
output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output dividers.
FEATURES
One differential 3.3V LVPECL output pair,
one differential feedback output pair
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: 40ps (maximum)
Static phase offset: 50ps ± 150ps
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PLL_SEL
CLK
nCLK
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
PLL
FB_IN
nFB_IN
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
SEL1
SEL2
SEL3
MR
8735AMI-21
PIN ASSIGNMENT
Q
0 nQ
1
QFB
nQFB
CLK
nCLK
MR
VCC
nFB_IN
FB_IN
SEL2
VEE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20 nc
19 SEL1
18 SEL0
17 VCC
16 PLL_SEL
1 5 VCCA
14 SEL3
1 3 VCCO
12 Q
11 nQ
ICS8735I-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
www.idt.com
1
REV. C AUGUST 11, 2010


Integrated Device Technology Electronic Components Datasheet

ICS8735I-21 Datasheet

ZERO DELAY CLOCK GENERATOR

No Preview Available !

ICS8735I-21 pdf
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1 CLK Input Pulldown Non-inverting differential clock input.
2
nCLK
Input Pullup Inverting differential clock input.
3
4, 17
5
6
MR
VCC
nFB_IN
FB_IN
Input
Power
Input
Input
Pulldown
Pullup
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ
and nQFB to go high. When LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to pin 9.
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to pin 10.
7
SEL2
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
8
9, 10
VEE
nQFB,
QFB
Power
Output
Negative supply pin.
Differential feedback outputs. LVPECL interface levels.
11, 12 nQ, Q Output
Differential clock outputs. LVPECL interface levels.
13 V
Power
CCO
Output supply pin.
14
SEL3
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
15
VCCA
Power
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
16 PLL_SEL Input Pullup When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
18
SEL0
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
19
SEL1
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
20 nc Unused
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8735AMI-21
www.idt.com
2
REV. C AUGUST 11, 2010


Part Number ICS8735I-21
Description ZERO DELAY CLOCK GENERATOR
Maker IDT
Total Page 16 Pages
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