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Integrated Device Technology Electronic Components Datasheet

ICS854S006I Datasheet

Differential-to-LVDS Fanout Buffer

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ICS854S006I pdf
Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
ICS854S006I
DATA SHEET
GENERAL DESCRIPTION
The ICS854S006I is a low skew, high perfor-
ICS mance 1-to-6 Differential-to-LVDS Fanout Buffer.
HiPerClockS™ The CLK, nCLK pair can accept most standard dif-
ferential input levels. The ICS854S006I is charac-
terized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output skew characteristic s
make the ICS854S006I ideal for those clock distribution
applications demanding well defined performance and
r e p e a t a b i l i t y.
FEATURES
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
Output skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK Pullup
nCLK Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
PIN ASSIGNMENT
nCLK
CLK
VDD
VDDO
Q0
nQ0
GND
Q1
nQ1
VDDO
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 GND
22 VDD
21 VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 Q4
15 VDDO
14 nQ3
13 Q3
ICS854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS854S006AGI REVISION B JANUARY 18, 2010
1
©2010 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS854S006I Datasheet

Differential-to-LVDS Fanout Buffer

No Preview Available !

ICS854S006I pdf
ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
nCLK
Input Pulldown Inverting differential clock input.
2
CLK
Input
Pullup Non-inverting differential clock input.
3, 22
4, 10, 15, 21
5, 6
VDD
VDDO
Q0, nQ0
Power
Power
Output
Positive supply pins.
Output supply pins.
Differential output pair. LVDS interface levels.
7, 18, 23, 24
GND
Power
Power supply ground.
8, 9
Q1, nQ1
Output
Differential output pair. LVDS interface levels.
11, 12
Q2, nQ2
Output
Differential output pair. LVDS interface levels.
13, 14
Q3, nQ3
Output
Differential output pair. LVDS interface levels.
16, 17
Q4, nQ4
Output
Differential output pair. LVDS interface levels.
19, 20
Q5, nQ5
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
CLK
nCLK
Outputs
Q0:Q5
nQ0:nQ5
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
ICS854S006AGI REVISION B JANUARY 18, 2010
2
©2010 Integrated Device Technology, Inc.


Part Number ICS854S006I
Description Differential-to-LVDS Fanout Buffer
Maker IDT
Total Page 15 Pages
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