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Integrated Device Technology Electronic Components Datasheet

ICS853S057I Datasheet

LVPECL/ECL Clock Data Multiplexer

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ICS853S057I pdf
4:1, Differential-To-3.3V, 2.5V LVPECL/ECL
Clock Data Multiplexer
ICS853S057I
DATA SHEET
General Description
The ICS853S057I is a 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL
Clock/Data Multiplexer which can operate up to 3GHz. The
ICS853S057I has 4 differential selectable clock input pairs. The
CLK, nCLK input pairs can accept LVPECL, LVDS, CML or SSTL
levels. The fully differential architecture and low propagation delay
make it ideal for use in clock distribution circuits. The multiplexer
select control inputs have ECL/LVPECL interface levels. The select
pins have internal pulldown resistors.
Features
High speed 4:1 differential muliplexer
One differential 3.3V, 2.5V LVPECL/ECL output
Four differential CLKx, nCLKx input pairs
Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, CML, SSTL
Maximum input/output frequency: 3GHz
Additive phase jitter, RMS @ 622.08MHz: 0.073ps (typical)
Part-to-part skew: 250ps (maximum)
Propagation delay: 615ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
CLK0 Pulldown
nCLK0 Pulldown
CLK1 Pulldown
nCLK1 Pulldown
CLK2 Pulldown
nCLK2 Pulldown
CLK3 Pulldown
nCLK3 Pulldown
SEL1 Pulldown
SEL0 Pulldown
VBB1
VBB2
00
(default)
01
10
11
Q
nQ
Pin Assignment
VCC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
1
2
3
4
5
6
7
8
9
10
20 VCC
19 SEL1
18 SEL0
17 VCC
16 Q
15 nQ
14 VCC
13 VBB1
12 VBB2
11 VEE
ICS853S057I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS853S057AGI REVISION A MAY 16, 2012
1
©2012 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS853S057I Datasheet

LVPECL/ECL Clock Data Multiplexer

No Preview Available !

ICS853S057I pdf
ICS853S057I Data Sheet
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 14, 17, 20
2
3
Name
VCC
CLK0
nCLK0
Type
Power
Input
Pulldown
Input
Pulldown
Description
Positive supply pins.
Non-inverting differential clock input.
Inverting differential clock input.
4
5
6
7
8
9
10, 11
12, 13
15, 16
18, 19
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
VEE
VBB2, VBB1
nQ, Q
SEL0, SEL1
Input
Input
Input
Input
Input
Input
Power
Output
Output
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pins.
ECL reference outputs.
Differential output pair. ECL/LVPECL interface levels.
Clock select inputs. ECL/LVPECL or LVCMOS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Function Tables
Table 3. Control Input Function Table
Control Inputs
Clock Out
SEL1
SEL0
Q, nQ
0
0 (default)
CLK0, nCLK0
0 1 CLK1, nCLK1
1 0 CLK2, nCLK2
1 1 CLK3, nCLK3
ICS853S057AGI REVISION A MAY 16, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS853S057I
Description LVPECL/ECL Clock Data Multiplexer
Maker IDT
Total Page 16 Pages
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