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Integrated Device Technology Electronic Components Datasheet

ICS853S01I Datasheet

2:1 Differential-to-LVPECL Multiplexer

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ICS853S01I pdf
2:1 Differential-to-LVPECL Multiplexer
ICS853S01I
DATA SHEET
General Description
The ICS853S01I is a high performance 2:1 Differential-to-LVPECL
Multiplexer. The ICS853S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS and CML
levels. The ICS853S01I is packaged in a small 3mm x 3mm 16
VFQFN package, making it ideal for use on space constrained
boards.
Features
One LVPECL output pair
Two selectable differential LVPECL clock inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML
Translates LVCMOS/LVTTL input signals to LVPECL levels by
using a resistor bias network on nPCLKx, nPCLKx
Part-to-part skew: 150ps (maximum)
Propagation delay: 490ps (maximum)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
Q
nQ
Pin Assignments
16 15 14 13
PCLK0 1
12 VEE
nPCLK0 2
11 Q
PCLK1 3
10 nQ
nPCLK1 4
9 VEE
5 6 78
ICS853S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
CLK_SEL
nc
VCC
1
2
3
4
5
6
7
8
16 nc
15 VEE
14 VEE
13 VCC
12 VEE
11 Q
10 nQ
9 VEE
ICS853S01I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS853S01AGI REVISION A OCTOBER 29, 2012
1
©2012 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS853S01I Datasheet

2:1 Differential-to-LVPECL Multiplexer

No Preview Available !

ICS853S01I pdf
ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 16
8, 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
CLK_SEL
nc
VCC
VEE
nQ, Q
Type
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Output
Input
Pulldown
Unused
Power
Power
Output
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Bias voltage.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS/LVTTL interface levels.
No connect.
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
37
Maximum
Units
pF
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
Input Selected
0 PCLK0, nPCLK0
1 PCLK1, nPCLK1
ICS853S01AGI REVISION A OCTOBER 29, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS853S01I
Description 2:1 Differential-to-LVPECL Multiplexer
Maker IDT
Total Page 23 Pages
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