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Integrated Device Technology Electronic Components Datasheet

ICS853S014I Datasheet

LVPECL/ECL Fanout Buffer

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ICS853S014I pdf
Low Skew, 1-to-5, Differential-to-2.5V, 3.3V
LVPECL/ECL Fanout Buffer
ICS853S014I
DATA SHEET
General Description
The ICS853S014I is a low skew, high performance 1-to-5, 2.5V/3.3V
Differential-to-LVPECL/ECL Fanout Buffer. The ICS853S014I has
two selectable clock inputs.
Guaranteed output and part-to-part skew characteristics make the
ICS853S014I ideal for those applications demanding well defined
performance and repeatability.
Features
Five differential LVPECL/ECL outputs
Two selectable differential LVPECL clock inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Output skew: 55ps (maximum)
Part-to-part skew: 100ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.10ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
nEN Pulldown
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
0
1
CLK_SEL Pulldown
VBB
D
Q
CLK
Pin Assignment
Q0 1
nQ0 2
20 VCC
19 nEN
Q1 3
18 VCC
Q0 nQ1 4 17 nPCLK1
Q2 5 16 PCLK1
nQ0
nQ2 6
15 VBB
Q1 Q3 7 14 nPCLK0
nQ3 8 13 PCLK0
nQ1 Q4 9 12 CLK_SEL
Q2 nQ4 10 11 VEE
nQ2 ICS853S014I
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.925mm package body
G Package
Q4
Top View
nQ4
ICS853S014AGI REVISION D MAY 23, 2013
1
©2013 Integrated Device Technology, Inc.



Integrated Device Technology Electronic Components Datasheet

ICS853S014I Datasheet

LVPECL/ECL Fanout Buffer

No Preview Available !

ICS853S014I pdf
ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2 Q0, nQ0 Output
Differential output pair. LVPECL/ECL interface levels.
3, 4 Q1, nQ1 Output
Differential output pair. LVPECL/ECL interface levels.
5, 6 Q2, nQ2 Output
Differential output pair. LVPECL/ECL interface levels.
7, 8 Q3, nQ3 Output
Differential output pair. LVPECL/ECL interface levels.
9, 10
Q4, nQ4 Output
Differential output pair. LVPECL/ECL interface levels.
11 VEE Power
Negative supply pin.
12
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects
PCLK0, nPCLK0 inputs. Single-ended LVPECL interface levels.
13
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
14
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
15 VBB Output
Bias voltage.
16
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock input.
17
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. VCC/2 default when left floating.
18, 20
19
VCC Power
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input. When
nEN
Input
Pulldown HIGH, Qx outputs are forced low, nQx outputs are forced high.
Single-ended LVPECL interface levels.
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter
RPULLDOWN Input Pulldown Resistor
RVCC/2
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
37
37
Maximum
Units
k
k
ICS853S014AGI REVISION D MAY 23, 2013
2
©2013 Integrated Device Technology, Inc.



Integrated Device Technology Electronic Components Datasheet

ICS853S014I Datasheet

LVPECL/ECL Fanout Buffer

No Preview Available !

ICS853S014I pdf
ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
nEN CLK_SEL
10
11
00
01
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, nPCLK0
PCLK1, nPCLK1
Outputs
Q0:Q4
nQ0:nQ4
Disabled; Low
Disabled; High
Disabled; Low
Disabled; High
Enabled
Enabled
Enabled
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as described in Table 3B.
nEN
nPCLK[0:1]
PCLK[0:1]
VPP
VDD/2
tS
nQ[0:4]
tPD
Q[0:4]
Figure 1. nEN Timing Diagram
VDD/2
tH
Table 3B. Clock Input Function Table
Inputs
PCLK0 or PCLK1
nPCLK0 or nPCLK1
01
10
0 Biased; NOTE 1
1 Biased; NOTE 1
Biased; NOTE 1
0
Biased; NOTE 1
1
Outputs
Q0:Q4
nQ0:nQ4
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section. Wiring the Differential Input to Accept Single-ended Levels.
ICS853S014AGI REVISION D MAY 23, 2013
3
©2013 Integrated Device Technology, Inc.




Part Number ICS853S014I
Description LVPECL/ECL Fanout Buffer
Maker IDT
Total Page 20 Pages
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