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Integrated Device Technology Electronic Components Datasheet

ICS81006I Datasheet

VCXO-TO-LVCMOS OUTPUTS

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VCXO-TO-LVCMOS OUTPUTS
ICS81006I
GENERAL DESCRIPTION
The ICS81006I is a high performance, low jitter/
ICS low phase noise VCXO and is a member of the
HiPerClockS™ HiPerClockS™ family of high performance clock
solutions from IDT. The ICS81006I works in
conjunction with a pullable crystal to generate
an output clock over the range of 12MHz - 40MHz and has
6 LVCMOS outputs, effectively integrating a fanout buffer
function.
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is ±100ppm around the
nominal crystal frequency. The VC control voltage range is
0 - VDD. The device is packaged in a small 4mm x 4mm
VFQFN package and is ideal for use on space constrained
boards typically encountered in ADSL/VDSL applications.
FEATURES
Six LVCMOS/LVTTL outputs, 20nominal
output impedance
Output Q5 can be selected for ÷1 or ÷2 frequency relative to
the crystal frequency
Output frequency range: 12MHz to 40MHz
Crystal pull range: ± 90ppm (typical)
Synchronous output enable places outputs in High-Z state
On-chip filter on VIN to suppress noise modulation of VCXO
V /V
DD DDO
combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
OE0 (Pullup)
VC LP Filter
SYNC
XTAL_IN
XTAL_OUT
VCXO
DIV_SEL_Q5 (Pulldown)
0: ÷1
1: ÷2
PIN ASSIGNMENT
Q0 20 19 18 17 16
XTAL_IN 1
15 GND
XTAL_OUT 2
14 Q2
Q1
VDD 3
13 VDDO
VC 4
12 Q3
Q2
DIV_SEL_Q5 5
11 GND
6 7 8 9 10
Q3
ICS81006I
20-Lead VFQFN
Q4 4mm x 4mm x 0.95 package body
K Package
Top View
Q5
OE1 (Pullup)
SYNC
IDT/ ICSVCXO-TO-LVCMOS OUTPUTS
1
ICS81006AKI REV A OCTOBER 2, 2006


Integrated Device Technology Electronic Components Datasheet

ICS81006I Datasheet

VCXO-TO-LVCMOS OUTPUTS

No Preview Available !

ICS81006I pdf
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
3 VDD Power
4 VC Input
Core supply pin.
Control voltage input.
5
DIV_SEL_Q5
Input
Pulldown
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH,
÷2, LVCMOS/LVTTL interface levels.
6
OE1
Input
Pullup
Output enable pin. When HIGH, Q5 output is enabled.
When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels.
7, 11, 15, 19
GND
Power
Power supply ground.
8, 10, 12,
14, 16, 18
Q5, Q4, Q3,
Q2, Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15typical output impedance.
9, 13, 17
20
VDDO
OE0
Power
Input
Pullup
Output supply pins.
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When
LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Input Capacitance OE0, OE1
CPD Power Dissipation Capacitance
R
PULLUP
RPULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
ROUT
Output Impedance
Test Conditions
VDD = VDDO = 3.465V
VDD = 3.465V or 2.625V,
VDDO = 2.625V
VDD = 3.465V or 2.625V,
VDDO = 2V
VDDO = 3.3V
VDDO = 2.5V
VDDO = 1.8V
Minimum
Typical
4
Maximum
3
Units
pF
pF
4 pF
6 pF
51 k
51 k
20
25
38
IDT/ ICSVCXO-TO-LVCMOS OUTPUTS
2
ICS81006AKI REV A OCTOBER 2, 2006


Part Number ICS81006I
Description VCXO-TO-LVCMOS OUTPUTS
Maker IDT
Total Page 14 Pages
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