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Elite Semiconductor
Elite Semiconductor

M12L64164A Datasheet Preview

M12L64164A Datasheet

1M x 16-Bit x 4-Bank SDRAM

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M12L64164A pdf
ESMT
SDRAM
M12L64164A
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
MRS cycle with address key programs
- CAS Latency (2 & 3)
M12L64164A-6T
166MHz TSOP II Non-Pb-free
- Burst Length (1, 2, 4, 8 & full page)
M12L64164A-7T
143MHz TSOP II Non-Pb-free
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
mDQM for masking
Auto & self refresh
o15.6 ยต s refresh interval
M12L64164A-6TG
M12L64164A-7TG
166MHz
143MHz
TSOP II
TSOP II
Pb-free
Pb-free
.cGENERAL DESCRIPTION
UThe M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
t416 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
eePIN ASSIGNMENT
hTop View
SVDD
taDQ0
VDDQ
DQ1
aDQ2
VSSQ
.D DQ3
DQ4
VDDQ
DQ5
w DQ6
VSSQ
w DQ7
VDD
w LDQM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
54 VSS
53 DQ15
52 VS SQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VS SQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
W E 16
39 U D Q M
C AS 17
38 CLK
R AS 18
37 CKE
CS 19
36 N C
A13 20
35 A11
A12 21
34 A9
A10/AP 22
33 A8
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VDD 27
28 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2005
Revision: 2.4
1/44



Elite Semiconductor
Elite Semiconductor

M12L64164A Datasheet Preview

M12L64164A Datasheet

1M x 16-Bit x 4-Bank SDRAM

No Preview Available !

M12L64164A pdf
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
M12L64164A
L(U)DQM
DQ
PIN FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
A12 , A13
RAS
CAS
WE
L(U)DQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2005
Revision: 2.4
2/44


Part Number M12L64164A
Description 1M x 16-Bit x 4-Bank SDRAM
Maker Elite Semiconductor
Total Page 30 Pages
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