is VIN(max) 2 = 186V . Often a 20% difference in capacitance could be observed between like
capacitors. Therefore a voltage rating margin of 25% should be considered.
Once the line drops below 50% of its peak voltage, the two capacitors are essentially placed in
parallel. The bus voltage VIN(min) is the lowest voltage value at the input of the buck converter. VIN(min)
at the minimum AC line voltage Vac(min) is,
VIN(min) = 2 × Vac(min) 2 = 2 × 85Vac 2 = 60V
At 60Hz, the total time of a half AC line cycle is 8.33ms. The power to the buck converter is derived
from the valley-fill capacitors when the AC line voltage is equal to or less than 50% of its peak voltage.
The hold up time for the capacitors equates to tHOLD = 1 3 × 8.33ms = 2.77ms . The valley-fill capacitor
value can then be calculated,
Pout VIN(min) × tHOLD
Therefore, C1 = C2 = 15μF . VDROOP is the voltage droop on the capacitors when they are delivering full
power to the buck converter. Ideally VDROOP should be set to less than VDROOP = VIN(min) − VLED(max) in
order to ensure continuous LED conduction at low line voltage. Nevertheless, VDROOP is set to be 20V
in the design example to avoid the need for very large valley-fill electrolytic capacitor.
A 20V VDROOP implies that the bus voltage VIN at the input of buck converter will drop to 40V during
part of the AC line cycle. As the buck regulator requires VIN to be greater than the LED stack voltage
(VLED(max)=59V) for regulation, the LED will be off during part of the AC line cycle. This has the effect of
reducing the actual output LED current at low AC input voltage. In the design example, the LED
current drops by approximately 20% from its nominal value at 85Vac (see Figure 4).
Setting the fixed off-time and switching frequency range
For fixed off-time operation, the switching frequency will vary subjected to the actual input voltage and
output LED conditions.
A nominal switching frequency fswi(nom) should be chosen. A high nominal switching frequency will
result in smaller inductor size, but could lead to increased switching losses in the circuit. A good
design practice is to choose a nominal switching frequency knowing that the switching frequency will
decrease as the line voltage drops and increases as the line voltage increases.
The fixed off-time tOFF can be computed as,
The off-time is programmed by timing resistor RT as shown in Figure 1. The value of RT is given by,
RT (kΩ) = tOFF(μs)× 25 − 22 = 13.9 × 25 − 22 = 326kΩ
A 330kΩ is selected for RT. Next, the two extremes of the variable switching frequency can be
1− 42V 373V
Issue 1 – January 2011
© Diodes Incorporated 2010