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Cypress Semiconductor Electronic Components Datasheet

W216 Datasheet

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

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W216 pdf
PRELIMINARY
W216
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• Single chip system FTG for Intel® 440BX AGPset and
VIA Apollo Pro-133
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• Seventeen SDRAM outputs provide support for 4
DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
CPU_F, 1:2
(MHz)
PCI_F, 0:5
(MHz)
1111
133.3
33.3 (CPU/4)
1110
124 31 (CPU/4)
1101
150 37.5 (CPU/4)
1100
140 35 (CPU/4)
1011
105 35 (CPU/3)
1010
110 36.7 (CPU/3)
1001
115 38.3 (CPU/3)
1000
120 40 (CPU/3)
0111
100 33.3 (CPU/3)
0110
Reserved
0101
112 37.3 (CPU/3)
0100
103 34.3 (CPU/3)
0011
66.8
33.4 (CPU/2)
0010
83.3
41.7 (CPU/2)
0001
75 37.5 (CPU/2)
0000
Reserved
Block Diagram
X1
X2
CLK_STOP#
XTAL
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
Stop
Clock
Control
SDRAMIN
PLL2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC_F
IOAPIC0
VDDQ2
CPU_F
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:15
16 SDRAM_F
Pin Configuration[1]
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ2
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPU_F
51 CPU1
50 VDDQ2
49 CPU2
48 GND
47 CLK_STOP#
46 SDRAM_F
45 VDDQ3
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDQ3
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDDQ3
30 24MHz/FS0
29 48MHz/FS1
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W216 Datasheet

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

No Preview Available !

W216 pdf
PRELIMINARY
W216
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU1:2
51, 49
O CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input
interface, see Tables 2 and 6. These outputs are affected by the CLK_STOP# input.
CPU_F
52 O Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Tables 2 and 6. This output is not affected by the CLK_STOP# input.
PCI1:5
11, 12, 13, 14, O PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input
16 interface, see Tables 2 and 6. These outputs are affected by the PCI_STOP# input.
PCI0/FS3
9 I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see Tables 2 and 6. This output is affected by the
PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and
PCI outputs.
PCI_F/MODE 8 I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input
interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When
an input, selects function of pin 3 as described in Table 1.
CLK_STOP#
47
I CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after com-
pleting a full clock cycle (23 CPU clock latency). When brought HIGH, affected outputs
start beginning with a full clock cycle (23 CPU clock latency).
IOAPIC_F
54 O Free-running IOAPIC Output: This output is a buffered version of the reference input
which is not affected by the CPU_STOP# logic input. Its swing is set by voltage applied
to VDDQ2.
IOAPIC0
55 I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set
by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW.
48MHz/FS1
29 I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power up, FS1
input will be latched, setting output frequencies as described in Table 2.
24MHz/FS0
30 I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input
will be latched, setting output frequencies as described in Table 2.
REF1/FS2
2 I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2
input will be latched, setting output frequencies as described in Table 2.
REF0
3 I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.
(PCI_STOP#)
The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to
remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of
PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides
a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins
(14.318 MHz).
SDRAMIN
17 I Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs
(SDRAM0:15, SDRAM_F).
SDRAM0:15 44, 43, 41, 40,
Buffered Outputs: These sixteen dedicated outputs provide copies of the signal pro-
39, 38, 36, 35, O vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
22, 21, 19, 18,
CLK_STOP# input is set LOW.
33, 32, 25, 24
SDRAM_F
SCLK
SDATA
46 O Free-Running Buffered Output: This output provides a single copy of the SDRAMIN
input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input.
28 I Clock pin for I2C circuitry.
27 I/O Data pin for I2C circuitry.
X1 5 I Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
X2 6 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
VDDQ3
1, 7, 15, 20,
31, 37, 45
P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers,
PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Con-
nect to 3.3V.
VDDQ2
50, 56
P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V
or 3.3V.
2


Part Number W216
Description Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Maker Cypress Semiconductor
Total Page 14 Pages
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