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Cypress Semiconductor Electronic Components Datasheet

W184 Datasheet

Six Output Peak Reducing EMI Solution

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W184 pdf
W184
Six Output Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable input to output frequency
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread reference output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 24-pin SSOP (Shrunk Small Outline
Package)
• Outputs may be selectively disabled
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz Fin 28 MHz
Crystal Reference Range.................... 8 MHz Fin 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
SS%
0
1
W184
Output
Fin Fout Fin – 1.25%
Fin Fout Fin – 3.75%
W184-5
Output
Fin + 0.625% Fin
0.625%
Fin + 1.875% Fin
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Table 3. Output Enable
Frequency Range
8 MHz FIN 10 MHz
10 MHz FIN 15 MHz
15 MHz FIN 18 MHz
18 MHz FIN 28 MHz
EN1
0
0
1
EN2
0
1
0
CLK0:4
Low
Low
Active
CLK5
Low
Active
Low
1 1 Active
Active
Simplified Block Diagram
3.3 or 5.0V
XTAL
Input
X1
X2
W184
Spread Spectrum
Outputs
(EMI suppressed)
3.3 or 5.0V
Oscillator or
Reference Input
W184
Spread Spectrum
Outputs
(EMI suppressed)
Pin Configuration
SSOP
REFOUT
FS2
X1
X2
GND
SS%
EN2
GND
CLK0
VDD
CLK1
CLK2
1
2
3
4
5
6
7
8
9
10
11
12
24 SSON#
23 RESET
22 FS1
21 VDD
20 VDD
19 NC
18 EN1
17 CLK5
16 VDD
15 CLK4
14 GND
13 CLK3
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 25, 2000, rev. *B



Cypress Semiconductor Electronic Components Datasheet

W184 Datasheet

Six Output Peak Reducing EMI Solution

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W184 pdf
W184
Pin Definitions
Pin Name
CLK0:5
CLKIN or X1
Pin No.
9, 11, 12, 13,
15, 17
3
NC or X2
SS%
4
6
Reset
23
REFOUT
14
EN1:2
SSON#
18, 7
24
FS1:2
VDD
22, 2
10, 16, 20, 21
Pin
Type
O
I
I
I
I
O
I
I
I
P
Pin Description
Modulated Frequency Outputs: Frequency modulated copies of the unmod-
ulated input clock (SSON# asserted).
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
Crystal Connection: If using an external reference, this pin must be left un-
connected.
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistors.
ModulationProfile Restart: A rising edge on this input restarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
Output Enable Select Pins: These pins control the activity of specific output
buffers. Set them to disable unused outputs using Table 3 as a guide.
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
Frequency Selection Bit 1 and 2: These pins select the frequency of opera-
tion. Refer to Table 1. These pins have internal pull-up resistors.
Power Connection: Connected to 3.3V or 5V power supply.
2



Cypress Semiconductor Electronic Components Datasheet

W184 Datasheet

Six Output Peak Reducing EMI Solution

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W184 pdf
W184
Overview
The W184 products are one series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low-
frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Functional Description
The W184 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W184 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS1:2 pins), the frequency range
can be set. Spreading percentage may be selected to 1.25%
or 3.75% (see Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
Clock Input
Reference Input
Freq.
Divider
Q
VDD
Phase
Detector
Charge
Pump
Σ
VCO
Post
Dividers
Feedback
Divider
P
Modulating
Waveform
PLL
CLKOUT
(EMI suppressed)
GND
Figure 1. Functional Block Diagram
3




Part Number W184
Description Six Output Peak Reducing EMI Solution
Maker Cypress Semiconductor
Total Page 8 Pages
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