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Cypress Semiconductor Electronic Components Datasheet

W170-01 Datasheet

Spread Aware/ Frequency Multiplier and Zero Delay Buffer

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W170-01 pdf
W170-01
Spread Aware™, Frequency Multiplier and Zero Delay Buffer
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Two outputs
• Configuration options allow various multiplication of
the reference frequency, refer to Table 1 to determine
the specific option which meets your multiplication
needs
• Available in 8-pin SOIC package
Key Specifications
Operating Voltage: ...........................3.3V±5% or 5.0V± 10%
Operating Range: .......................20 MHz < fOUT1 < 133 MHz
Absolute Jitter: ......................................................... ±500 ps
Output to Output Skew: .............................................. 250 ps
Propagation Delay: ................................................... ±350 ps
Propagation delay is affected by input rise time.
Table 1. Configuration Options
FBIN
FS0 FS1
OUT1
OUT1
0
0 2 X REF
OUT1
1
0 4 X REF
OUT1
0
1
REF
OUT1
1
1 8 X REF
OUT2
0
0 4 X REF
OUT2
1
0 8 X REF
OUT2
0
1 2 X REF
OUT2
1
1 16 X REF
OUT2
REF
2 X REF
REF/2
4 X REF
2 X REF
4 X REF
REF
8 X REF
Block Diagram
Pin Configuration
FBIN
FS0
÷Q
FS1
External feedback connection to
OUT1 or OUT2, not both
FBIN
IN
GND
FS0
1
2
3
4
8 OUT2
7 VDD
6 OUT1
5 FS1
IN
Reference
Input
Phase
Detector
Charge
Pump
Loop
Filter
Output
Buffer
VCO
÷2
Output
Buffer
OUT1
OUT2
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 28, 1999, rev. **



Cypress Semiconductor Electronic Components Datasheet

W170-01 Datasheet

Spread Aware/ Frequency Multiplier and Zero Delay Buffer

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W170-01 pdf
W170-01
Pin Definitions
Pin Name
IN
FBIN
Pin No.
2
1
OUT1
OUT2
VDD
GND
FS0:1
6
8
7
3
4, 5
Pin
Type
I
I
O
O
P
P
I
Pin Description
Reference Input: The output signals will be synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to
ensure proper functionality. If the trace between FBIN and the output pin being used
for feedback is equal in length to the traces between the outputs and the signal desti-
nations, then the signals received at the destinations will be synchronized to the REF
signal input (IN).
Output 1: The frequency of the signal provided by this pin is determined by the feed-
back signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Output 2: The frequency of the signal provided by this pin is one-half of the frequency
of OUT1. See Table 1.
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a
0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter
performance.
Ground Connection: Connect all grounds to the common system ground plane.
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 1.
Overview
Spread Aware
The W170-01 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing max-
imum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
How to Implement Zero Delay,and Inserting Other Devices
in Feedback Path.
The W170-01 is a pin-compatible upgrade of the Cypress
W42C70-01. The W170-01 addresses some application de-
pendent problems experienced by users of the older device.
Most importantly, it addresses the tracking skew problem in-
duced by a reference which has Spread Spectrum Timing en-
abled on it.
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.
2



Cypress Semiconductor Electronic Components Datasheet

W170-01 Datasheet

Spread Aware/ Frequency Multiplier and Zero Delay Buffer

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W170-01 pdf
W170-01
CA
G
10 µF
Ferrite
Bead
C8
0.01 µF
V+ Power Supply Connection
G
FBIN
IN
GND
FS0
1
2
3
G
4
OUT 2
8
VDD
7
OUT 1
6
5
22
OUTPUT 2
C9 = 0.1 µF
G
22
OUTPUT 1
FS1
Figure 1. Schematic/Suggested Layout
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feed back and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay in the ASIC/Buffer must be accounted for.
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Inserting Other Devices in Feedback Path
Figure 2. 6 Output Buffer in the Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals up to the signal coming from
3




Part Number W170-01
Description Spread Aware/ Frequency Multiplier and Zero Delay Buffer
Maker Cypress Semiconductor
Total Page 6 Pages
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