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Cypress Semiconductor Electronic Components Datasheet

W164 Datasheet

Spread Spectrum Desktop/Notebook System Frequency Generator

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W164 pdf
W164
Spread Spectrum Desktop/Notebook System
Frequency Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Reduces measured EMI by as much as 10 dB
• I2C programmable to 153 MHz (16 selectable
frequencies)
• Two skew-controlled copies of CPU output
• SEL100/66# selects CPU frequency (100 or 66.8 MHz)
• Seven copies of PCI output (synchronous w/CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz output is determined by resistor
straps on power-up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Supply Voltages:....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: ........................................... 200 ps
CPU, PCI Output Edge Rate: ......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: .............................. 1 to 4 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA ................ 250-kpull-up
Note: Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
Table 1. Pin Selectable Frequency
SEL100/66#
CPU(0:1)
1 100 MHz
0 66.8 MHz
PCI
33.3 MHz
33.4 MHz
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
VDDQ3
REF2X/SEL48#
GND
VDDQ3
IOAPIC
VDDQ2
CPU0
CPU1
GND
Pin Configuration
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 REF2X/SEL48#
26 VDDQ3
25 VDDQ2
24 IOAPIC
23 VDDQ2
22 CPU0
21 CPU1
20 VDDQ3
19 GND
18 SDATA
17 SCLOCK
16 SEL100/66#
15 GND
100/66#_SEL
PLL 1
÷2/÷3/÷4
SDATA
SCLOCK
I2C
LOGIC
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
GND
PLL2
VDDQ3
48MHz
24/48MHz
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 16, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W164 Datasheet

Spread Spectrum Desktop/Notebook System Frequency Generator

No Preview Available !

W164 pdf
W164
Pin Definitions
Pin Name
CPU0:1
Pin
No.
22, 21
PCI1:6
PCI_F
5, 6, 7, 8, 10,
11, 4
IOAPIC
24
48MHz
13
24/48MHz
REF2X/SEL48#
14
27
SEL100/66#
SDATA
SCLOCK
X1
X2
VDDQ3
VDDQ2
GND
16
18
17
1
2
9, 12, 20, 26
23, 25
3, 15, 19, 28
Pin
Type
O
O
O
O
O
I/O
I
I/O
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
VDDQ3.
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.
I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
page 1.
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kpull-up resistor.
I2C Clock Pin: The I2C data clock should be presented to this input as described in
the I2C section of this data sheet.
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
Ground Connections: Connect all ground pins to the common system ground
plane.
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input
select pins.
An external 10-kstrappingresistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to 0,connection to VDD sets a latch to 1.Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping re-
sistor on the l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic 0or 1condition of the
l/O pin is then latched. Next the output buffer is enabled which
converts the l/O pin into an operating clock output. The 2-ms
timer is started when VDD reaches 2.0V. The input bit can only
be reset by turning VDD off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 25(nominal) which is minimally affected by
the 10-kstrap to ground or VDD. As with the series termina-
tion resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the intercon-
necting trace short. The trace from the resistor to ground or
VDD should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
2


Part Number W164
Description Spread Spectrum Desktop/Notebook System Frequency Generator
Maker Cypress Semiconductor
Total Page 11 Pages
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