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Cypress Semiconductor Electronic Components Datasheet

W163 Datasheet

Spread Aware/ Zero Delay Buffer

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W163 pdf
W163
Spread Aware™, Zero Delay Buffer
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Outputs may be three-stated
• Available in 8-pin SOIC package
• Extra strength output drive available (-15 version)
• Internal feedback maximized the number of outputs
available in 8-pin package
Key Specifications
Operating Voltage: ................................................ 3.3V±10%
Operating Range: ................................ 10 < fOUT < 133 MHz
Cycle-to-Cycle Jitter: .................................................. 200 ps
Output-to-Output Skew: .............................................. 250 ps
Device-to-Device Skew:............................................... 700 ps
Propagation Delay: ...................................................... 350 ps
Block Diagram
Pin Configuration
REF
PLL
SOIC
REF
1
8 QFB
Q0 2
7 Q3
QFB
Q1 3
6 VDD
Q0
GND
4
5 Q2
Q1
Q2
Q3
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 21, 2000, rev. *A


Cypress Semiconductor Electronic Components Datasheet

W163 Datasheet

Spread Aware/ Zero Delay Buffer

No Preview Available !

W163 pdf
W163
Pin Definitions
Pin Name
REF
Q0:3
QFB
VDD
GND
Pin No.
1
2, 3, 5, 7
8
6
4
Pin
Type
I
O
O
P
P
Pin Description
Reference Input: The output signals Q0:3 will be synchronized to this signal
unless the device is programmed to bypass the PLL.
Outputs: These signals will be synchronous and of equal frequency to the signal
input at pin 1.
Feedback Output: This output signal does not vary from signals Q0:3 in function,
but is noted as the signal used to establish the propagation delay of nearly 0.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect all grounds to the common system ground
plane.
Overview
The W163 products are five-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide five copies of that same signal out. The internal
feedback to the PLL provides outputs in phase with the refer-
ence inputs.
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress Application note titled, EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.
Schematic
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
REF
Q0
Q1
GND
QFB
Q3
VDD
Q2
Ferrite
Bead
0.1 µF 10 µF
VDD
2


Part Number W163
Description Spread Aware/ Zero Delay Buffer
Maker Cypress Semiconductor
Total Page 4 Pages
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