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Cypress Semiconductor Electronic Components Datasheet

W158 Datasheet

Spread Spectrum System Frequency Synthesizer

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W158 pdf
W158
Spread Spectrum System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Intel® CK98 Specification compliant
• 0.5% downspread outputs deliver up to 10 dB lower EMI
• Four skew-controlled copies of CPU output
• Eight copies of PCI output (synchronous w/CPU output)
• Four copies of 66-MHz fixed frequency 3.3V clock
• Two copies of CPU/2 outputs for synchronous memory
reference
• Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
• One copy of 48-MHz USB output
• Two copies of 14.31818-MHz reference clock
• Programmable to 133- or 100-MHz operation
• Power management control pins for clock stop and shut
down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ...................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1
X2
CPU_STOP#
SPREAD#
SEL0
SEL1
SEL133/100#
XTAL
OSC
PLL 1
2
REF0:1
STOP
Clock
Logic
÷2
÷2/÷1.5
STOP
Clock
Logic
4
CPU0:3
2
CPUdiv2_0:1
4
3V66_0:3
PWRDWN#
PCI_STOP#
÷2
Power
Down
Logic
STOP
Clock
Logic
÷2
1
PCI_F
7
PCI1:7
3
IOAPIC0:2
CPU Output Jitter: ...................................................... 150 ps
CPUdiv2, IOAPIC Output Jitter: ..................................250 ps
48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ...........................250 ps
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset: ............ 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-kpull-up
resistors
Table 1. Pin Selectable Frequency[1]
SEL133/100#
CPU0:3 (MHz)
PCI
1
133 MHz
33.3 MHz
0
100 MHz
33.3 MHz
Note:
1. See Table 2 for complete mode selection details.
Pin Configuration
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ2
55 IOAPIC2
54 IOAPIC1
53 IOAPIC0
52 GND
51 VDDQ2
50 CPUdiv2_1
49 CPUdiv2_0
48 GND
47 VDDQ2
46 CPU3
45 CPU2
44 GND
43 VDDQ2
42 CPU1
41 CPU0
40 GND
39 VDDQ3
38 GND
37 PCI_STOP#
36 CPU_STOP#
35 PWRDWN#
34 SPREAD#
33 SEL1
32 SEL0
31 VDDQ3
30 48MHz
29 GND
Three-state
Logic
PLL2
Intel is a registered trademark of Intel Corporation.
1
48MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 12, 1999, rev. **


Cypress Semiconductor Electronic Components Datasheet

W158 Datasheet

Spread Spectrum System Frequency Synthesizer

No Preview Available !

W158 pdf
W158
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU0:3
41, 42, 45, 46 O CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1 49, 50
O Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Di-
rect RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing
is set by the voltage applied to VDDQ2.
PCI1:7
9, 11, 12, 14,
15, 17, 18
O PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to
the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs
are stopped when PCI _STOP# is held LOW.
PCI_F
8 O PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock.
Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the state
of PCI_STOP#.
REF0:1
2, 3 O 14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock.
IOAPIC0:2
53, 54, 55
O I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing
is set by the power connection to VDDQ2.
48MHz
30 O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:3
21, 22, 25, 26 O 66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled
by voltage applied to VDDQ3.
SEL0:1
32, 33
I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output
modes.
SEL133/100#
28
I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output fre-
quency as shown in Table 1.
X1 5 I Crystal Connection or External Reference Frequency Input: Connect to either a
14.318-MHz crystal or an external reference signal.
X2 6 O Crystal Connection: An output connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
SPREAD#
34 I Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
PWRDWN# 35 I Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that re-
quests the device to enter power-down mode.
CPU_STOP#
36
I Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input.
PCI_STOP#
37
I Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
PCI outputs except PCI_F when held LOW.
VDDQ3
4, 10, 16, 23,
27, 31, 39
P Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer,
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to
3.3V supply.
VDDQ2
43, 47, 51, 56 P Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers. Con-
nect to 2.5V supply.
GND
1, 7, 13, 19, G Ground Connection: Connect all ground pins to the common system ground plane.
20, 24, 29, 38,
40, 44, 48, 52
Overview
The W158 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel architec-
ture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W158 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also pro-
vides skew-controlled PCI and IOAPIC clocks synchronous to
CPU clock, 48-MHz Universal Serial Bus (USB) clock, and rep-
licates the 14.31818-MHz reference clock.
All CPU, PCI, and IOAPIC clocks can be synchronously mod-
ulated for spread spectrum operations. Cypress employs pro-
prietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. Spread Spectrum modulation is enabled by
the active LOW control signal SPREAD#.
The W158 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
2


Part Number W158
Description Spread Spectrum System Frequency Synthesizer
Maker Cypress Semiconductor
Total Page 12 Pages
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