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Cypress Semiconductor Electronic Components Datasheet

W149 Datasheet

440BX AGPset Spread Spectrum Frequency Synthesizer

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W149 pdf
W149
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Spread Spectrum feature always enabled
• I2C™ interface for programming
• Power management control inputs
• Smooth CPU frequency switching from 66.8–124 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: ..................................................................... 3.3V±5%
VDDQ2: ..................................................................... 2.5V±5%
SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ.
Table 1. Mode Input Table[1]
Mode
Pin 2
0 PCI_STOP#
1 REF0
Table 2. Pin Selectable Frequency
Input Address CPU0:1
FS2 FS1 FS0 (MHz)
PCI_F, 1:5
(MHz)
111
100 33.3 (CPU/3)
110
(Reserved)
101
100 33.3 (CPU/3)
100
103 34.3 (CPU/3)
011
66.8 33.4 (CPU/2)
010
83.3 41.7 (CPU/2)
001
66.8 33.4 (CPU/2)
000
124 41.3 (CPU/3)
Spread
%
–0.5
±0.5
–0.5
–0.5
–0.5
±0.5
–0.5
Logic Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
PLL 1
÷2/÷3
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
PCI_F/MODE
PCI1
PCI2
PCI3
PCI4
Pin Configuration[2]
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU0
43 CPU1
42 VDDQ2
41 OE
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
SDATA
SCLK
I2C
Logic
PCI5
PLL2
VDDQ3
48MHz/FS0
÷2
SDRAMIN
24MHz/FS1
VDDQ3
SDRAM0:12
13
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Notes:
1. Mode input latched at power-up.
2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 31, 2000 rev. *A



Cypress Semiconductor Electronic Components Datasheet

W149 Datasheet

440BX AGPset Spread Spectrum Frequency Synthesizer

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W149 pdf
W149
Pin Definitions
Pin Name
Pin No. Pin Type
Pin Description
CPU0:1
44, 43
O CPU Clock Outputs: See Tables 2 and 6 for detailed frequency information. Output
voltage swing is controlled by voltage applied to VDDQ2.
PCI1:5
8, 10, 11, 12,
O PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by
13 the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F/MODE
7
I/O Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial
input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#
input. Upon power-up the mode input will be latched, which will determine the func-
tion of pin 2, REF0/(PCI_STOP#). See Table 1.
OE 41 I Output Enable Input: When brought LOW, all outputs are placed in a high-imped-
ance state. When brought HIGH, all clock outputs activate.
IOAPIC
47 O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48MHz/FS0
26
I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up,
FS0 input will be latched, which will set clock frequencies as described in Table 2.
This output does not have the Spread Spectrum feature.
24MHz/FS1
25
I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input
will be latched, which will set clock frequencies as described in Table 2. This output
does not have the Spread Spectrum feature.
REF1/FS2 46 I/O I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched
which will set clock frequencies as described in Table 2. When an output, this pin
provides a fixed clock signal equal in frequency to the reference signal provided at
the X1/X2 pins.
REF0/
(PCI_STOP#)
2
I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the
MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5
outputs when HIGH and causes them to remain at logic 0 when LOW. The
PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on
the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal
equal in frequency to the reference signal provided at the X1/X2 pins.
SDRAMIN
15
I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
SDRAM0:12 38, 37, 35,
Buffered Outputs: These thirteen dedicated outputs provide copies of the signal
34, 32, 31,
O provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deacti-
29, 28, 21,
vated when CLK_STOP# input is set LOW.
20, 18, 17, 40
SCLK
24 I Clock pin for I2C circuitry.
SDATA
23 I/O Data pin for I2C circuitry.
X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19,
27, 30, 36
P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to
3.3V supply.
VDDQ2
42, 48
P Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect
to 2.5V, or 3.3V.
GND
3, 9, 16, 22,
33, 39, 45
G Ground Connections: Connect all ground pins to the common system ground
plane.
2



Cypress Semiconductor Electronic Components Datasheet

W149 Datasheet

440BX AGPset Spread Spectrum Frequency Synthesizer

No Preview Available !

W149 pdf
W149
Overview
The W149 was developed as a single chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX AGPset
FTGs, the W149 adds a thirteen output buffer, supporting
SDRAM DIMM modules in conjunction with the chipset.
Cypress proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. This feature
reduces the peak EMI measurements of not only the output
signals and their harmonics, but also of any other clock signals
that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 25, 26, 46 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-kstrappingresistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to 0, connection to VDD sets a latch to 1. Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W149 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the four I/O pins (7,
25, 26, 46) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull each pin and its associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
of the 2-ms period, the established logic 0or 1condition of
the l/O pin is latched. Next the output buffer is enabled, con-
verting the l/O pins into operating clock outputs. The 2-ms tim-
er starts when VDD reaches 2.0V. The input bits can only be
reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output is <40(nominal), which is minimally af-
fected by the 10-kstrap to ground or VDD. As with the series
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
W149
Power-on
Reset
Timer
VDD
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 k
/RDG 2SWLRQ 
10 k
/RDG 2SWLRQ 
2XWSXW 6WUDSSLQJ 5HVLVWRU
6HULHV 7HUP LQDWLRQ 5HVLVWRU
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
W149
Power-on
Reset
Timer
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 k
VDD Output Strapping Resistor
Series Termination Resistor
R Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
3




Part Number W149
Description 440BX AGPset Spread Spectrum Frequency Synthesizer
Maker Cypress Semiconductor
Total Page 14 Pages
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