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Cypress Semiconductor Electronic Components Datasheet

W147 Datasheet

Frequency Generator for Integrated Core Logic

No Preview Available !

W147 pdf
PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Three copies of CPU clock at 66/100 MHz
• Nine copies of 100-MHz SDRAM clocks
• Eight copies of PCI clock
• Two copies of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video dot clock
• Two copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power-down control
• I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps
CPU, 3V66 Output Skew: ............................................175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
SEL1
SEL0
00
01
10
11
Function
Three-state
Test
66-MHz CPU
100-MHz CPU
Block Diagram
X1
X2
SDATA
SCLK
SEL0:1
XTAL
OSC
PLL REF FREQ
I2C
Logic
D i vi d e r,
D el a y,
and
Phase
Control
Logic
PLL 1
PWRDWN#
VDDQ3
REF/APICDIV
VDDQ2
CPU0:1
2
CPU2_ITP
APIC0:1
2
VDDQ3
3V66_0:1
2
PCI0_ICH
PCI1:7
7
DCLK
SDRAM0:7
8
PLL2
VDDQ3
USB
DOT
Pin Configuration
REF/APICDIV
VDDQ3
X1
X2
GND
GND
3V66_0
3V66_1
VDDQ3
VDDQ3
PCI0_ICH
PCI1
PCI2
GND
PCI3
PCI4
GND
PCI5
PCI6
PCI7
VDDQ3
VDD3
GND
GND
USB
DOT
VDDQ3
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GND
55 APIC0
54 APIC1
53 VDDQ2
52 CPU0
51 VDDQ2
50 CPU1
49 CPU2_ITP
48 GND
47 GND
46 SDRAM0
45 SDRAM1
44 VDDQ3
43 SDRAM2
42 SDRAM3
41 GND
40 SDRAM4
39 SDRAM5
38 VDDQ3
37 SDRAM6
36 SDRAM7
35 GND
34 DCLK
33 VDDQ3
32 PWRDWN#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **



Cypress Semiconductor Electronic Components Datasheet

W147 Datasheet

Frequency Generator for Integrated Core Logic

No Preview Available !

W147 pdf
PRELIMINARY
W147G
Pin Definitions
Pin Name
REF/APICDIV
Pin No.
1
X1
X2
PCI0_ICH,
PCI1:7
3V66_0:1
USB
DOT
SEL0:1
PWRDWN#
CPU2_ITP,
CPU0:1
SDRAM0:7,
DCLK
APIC0:1
3
4
11, 12, 13, 15,
16, 18, 19. 20
7, 8
25
26
28, 29
32
49, 52, 50
46, 45, 43, 42,
40, 39, 37, 36,
34
55, 54
SDATA
SCLK
VDDQ3
VDD3
VDDQ2
GND
30
31
2, 9, 10, 21, 27,
33, 38, 44
22
51, 53
5, 6, 14, 17, 23,
24, 35, 41, 47,
48, 56
Pin
Type
I/O
I
I
O
O
O
O
I
I
O
O
Pin Description
Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select
strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs
at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed.
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection as an external reference frequency input.
Crystal Output: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually
turned off via I2C interface.
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
Clock Function Selection pins: LVTTL-compatible input to select device func-
tions. See Table 1 for detailed descriptions.
Power Down Control: LVTTL-compatible asynchronous input that places the de-
vice in power-down mode when held LOW.
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration
of SEL0:1. Voltage swing set by VDDQ2.
SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be
individually turned off via I2C interface.
O Sychronous APIC Clock Outputs: Clock outputs running divide synchronous
with the PCI clock outputs. Output frequency is controlled by the strap option on
REF. Voltage swing set by VDDQ2.
I/O Data pin for I2C circuitry.
I Clock pin for I2C circuitry.
P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
P 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V.
P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
2



Cypress Semiconductor Electronic Components Datasheet

W147 Datasheet

Frequency Generator for Integrated Core Logic

No Preview Available !

W147 pdf
PRELIMINARY
W147G
W147G
Power-on
Reset
Timer
VDD
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 k
(Load Option 1)
10k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W147G is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/APICDIV is a dual purpose l/O pin. Upon power-up the
pin acts as a logic input. If the pin is strapped to a LOW state
externally, APIC clock outputs will run divide synchronously at
half PCI clock speed. If it is pulled HIGH, APIC clock will run
synchronous to PCI clocks. An external 10-kstrapping resis-
tor should be used. Figure 1 shows a suggested method for
strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
SEL0:1. Specific outputs available at each pin is detailed in
Table 2 below. The SEL0 pin requires a 220pull-up resistor
to 3.3V for the W147G to sense the maximum host bus fre-
quency of the processor and configure itself accordingly.
Table 2. CK Whitney Truth Table
SEL1 SEL0
CPU
SDRAM
3V66
PCI 48MHz
REF
0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z
0 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK
1 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz
1 1 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz
Notes:
1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
2. Provided for board level bed of nailstesting.
3. Normalmode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
APIC[1]
Hi-Z
TCLK/6
16.67 MHz
16.67 MHz
Notes
2
4, 5
3, 6, 7
3, 6, 7
3




Part Number W147
Description Frequency Generator for Integrated Core Logic
Maker Cypress Semiconductor
Total Page 12 Pages
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