Architecture and Operation
This section presents detailed information about the most important sensor blocks.
Figure 1. Block Diagram of the IBIS5-B-1300 Image Sensor
Figure 1 shows the architecture of the IBIS5-B-1300 image
wwswen.Dsaotra.SIhteceot4nUs.icsotsmbasically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
curtain shutter mode, use the right Y-addressing register for the
reset pointer in single and double slope operation to reset one
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (like start/stop integration, line
and frame sync signals, and others.) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
A description of the pixel architecture and the color filter array
The pixel architecture used in the IBIS5-B-1300 is a 4-transistor
pixel as shown in Figure 2. Implement the pixel using the high fill
factor technique as patented by Cypress (US patent No.
6,225,670 and others). The 4T-pixel features a snapshot shutter
but can also emulate the 3T-pixel by continuously closing
sampling switch M2. Using M4 as a global sample transistor for
all pixels enables the snapshot shutter mode. Due to this pixel
architecture, integration during read out is not possible in
synchronous shutter mode.
Figure 2. Architecture of the 4T-pixel
Document #: 38-05710 Rev. *C
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