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Cypress Semiconductor Electronic Components Datasheet

CYII5FM1300AB Datasheet

1.3 MP CMOS Image Sensor

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CYII5FM1300AB pdf
IBIS5-B-1300 CYII5FM1300AB
1.3 MP CMOS Image Sensor
Description
The IBIS5-B-1300 is a solid state CMOS image sensor that
integrates the functionality of complete analog image acquisition,
digitizer, and digital signal processing system on a single chip.
This 1.3-mega pixel (1280 x 1024) CMOS active pixel sensor
dedicated to industrial vision applications features both rolling
and snapshot (or global) shutter. Full frame readout time is 36 ms
(max. 27.5 fps), and readout speed are boosted by windowed
region of interest (ROI) readout. Another feature includes the
double and multiples slope functionality to capture high dynamic
range scenes. The sensor is available in a Monochrome version
or Bayer (RGB) patterned color filter array.
User programmable row and column start/stop positions allow
windowing down to a 2x1 pixel window for digital zoom. Sub
sampling or viewfinder mode reduces resolution while
maintaining the constant field of view and an increased frame
rate. An on-chip analog signal pipeline processes the analog
video output of the pixel array. Double sampling (DS) eliminates
the fixed pattern noise. The programmable gain and offset
amplifier maps the signal swing to the ADC input range. A 10-bit
ADC converts the analog data to a 10-bit digital word stream. The
sensor uses a 2-wire, I2C™-compatible interface, a 3-wire serial
parallel (SPI) interface, or a 16-bit parallel interface. It operates
with a 3.3V power supply and requires only one master clock for
operation up to 40 MHz. It is housed in an 84-pin ceramic LCC
package.
Applications
n Machine vision
n Inspection
wwn wR.DoabtoaStichseet4U.com
n Traffic monitoring
Table 1. Key Performance Parameters
Parameter
Active pixels
Pixel size
Optical format
Shutter type
Typical Value
1280 (H) x 1024 (V)
6.7 µm x 6.7 µm
2/3 inch
Snapshot (global) shutter
rolling shutter
Maximum data rate /
master clock
Frame rate
ADC resolution
40 MPS / 40 MHz
27 fps (1280 x 1024)
106 fps (640 x 480)
10-bit, on-chip
Sensitivity (@ 650 nm)
S/N ratio
Full well charge
715 V.m2/W.s
8.40 V/lux.s
64 dB
62.500 e–
Temporal noise
Dark current
High dynamic range
Supply voltage
Power consumption
Operating temperature
Color filter array
Packaging
40 e–
7.22 mV/s
Multiple slope
Analog: 3.0V–4.5V
Digital: 3.3V
I/O: 3.3V
175 mW
–30°C to +65°C
Mono
RGB Bayer pattern
84-pins LCC
IBIS5-B-1300
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05710 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 27, 2007


Cypress Semiconductor Electronic Components Datasheet

CYII5FM1300AB Datasheet

1.3 MP CMOS Image Sensor

No Preview Available !

CYII5FM1300AB pdf
IBIS5-B-1300 CYII5FM1300AB
Architecture and Operation
This section presents detailed information about the most important sensor blocks.
Floor Plan
Figure 1. Block Diagram of the IBIS5-B-1300 Image Sensor
Y-left
addressing
Pixel
Imager core
Sensor
Y-right
addressing
Reset
C
Sample
Select
Column output
Pixel core
Column amplifiers
Analog multiplexer
X-addressing
Output
amplifier
Sequencer
ADC
System clock
40 MHz
External
connection
Figure 1 shows the architecture of the IBIS5-B-1300 image
wwswen.Dsaotra.SIhteceot4nUs.icsotsmbasically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
curtain shutter mode, use the right Y-addressing register for the
reset pointer in single and double slope operation to reset one
pixel row.
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (like start/stop integration, line
and frame sync signals, and others.) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
Pixel
A description of the pixel architecture and the color filter array
follows.
Architecture
The pixel architecture used in the IBIS5-B-1300 is a 4-transistor
pixel as shown in Figure 2. Implement the pixel using the high fill
factor technique as patented by Cypress (US patent No.
6,225,670 and others). The 4T-pixel features a snapshot shutter
but can also emulate the 3T-pixel by continuously closing
sampling switch M2. Using M4 as a global sample transistor for
all pixels enables the snapshot shutter mode. Due to this pixel
architecture, integration during read out is not possible in
synchronous shutter mode.
Figure 2. Architecture of the 4T-pixel
M1 reset
C
M2
sample
M3 mux
M4
column
output
Document #: 38-05710 Rev. *C
Page 2 of 40


Part Number CYII5FM1300AB
Description 1.3 MP CMOS Image Sensor
Maker Cypress Semiconductor
Total Page 30 Pages
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