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Cypress Semiconductor Electronic Components Datasheet

CY8CPLC20 Datasheet

Powerline Communication Solution

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CY8CPLC20 pdf
CY8CPLC20
Powerline Communication Solution
Features
Powerline Communication Solution
Integrated Powerline Modem PHY
Frequency Shift Keying Modulation
Configurable baud rates up to 2400 bps
Powerline Optimized Network Protocol
Integrates Data Link, Transport, and Network Layers
Supports Bidirectional Half Duplex Communication
8-bit CRC Error Detection to Minimize Data Loss
I2C enabled Powerline Application Layer
Supports I2C Frequencies of 50, 100, and 400 kHz
Reference Designs for 110V/240V AC and 12V/24V AC/DC
Powerlines
Reference Designs comply with CENELEC EN
50065-1:2001 and FCC Part 15
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
Two 8x8 Multiply, 32-Bit Accumulate
Programmable System Resources (PSoC® Blocks)
12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPITM Masters or Slaves
• Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Logic Block Diagram
Flexible On-Chip Memory
32 KB Flash Program Storage 50,000 Erase or Write Cycles
2 KB SRAM Data Storage
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink, 10 mA Source on all GPIO
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
Up to 12 Analog Inputs on GPIO
Configurable Interrupt on all GPIO
Additional System Resources
I2C Slave, Master, and Multi-Master to 400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software (PSoC Designer™)
Full Featured In-Circuit Emulator (ICE) and Programmer
Full Speed Emulation
Complex Breakpoint Structure
128 KB Trace Memory
Complex Events
C Compilers, Assembler, and Linker
Powerline Communication Solution
Powerline Network
Protocol
Physical Layer FSK
Modem
PLC Core
Embedded Application
Programmable
System Resources
Digital and Analog
Peripherals
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
Powerline Transceiver Packet
AC/DC Powerline Coupling Circuit
(110V/240V AC, 12V/24V AC/DC etc.)
Powerline
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-48325 Rev. *E
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 05, 2009
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Cypress Semiconductor Electronic Components Datasheet

CY8CPLC20 Datasheet

Powerline Communication Solution

No Preview Available !

CY8CPLC20 pdf
CY8CPLC20
1. PLC Functional Overview
The CY8CPLC20 is an integrated Powerline Communication
(PLC) chip with the Powerline Modem PHY and Network
Protocol Stack running on the same device. Apart from the PLC
core, the CY8CPLC20 also offers Cypress's revolutionary PSoC
technology that enables system designers to integrate multiple
functions on the same chip.
1.1 Robust Communication using Cypress’s PLC
Solution
Powerlines are available everywhere in the world and are a
widely available communication medium for PLC technology.
The pervasiveness of powerlines also makes it difficult to predict
the characteristics and operation of PLC products. Because of
the variable quality of powerlines around the world, imple-
menting robust communication has been an engineering
challenge for years. The Cypress PLC solution enables secure
and reliable communications. Cypress PLC features that enable
robust communication over powerlines include:
Integrated Powerline PHY modem with optimized filters and
amplifiers to work with lossy high voltage and low voltage
powerlines.
Powerline optimized network protocol that supports bidirec-
tional communication with acknowledgement-based signaling.
In case of data packet loss due to bursty noise on the powerline,
the transmitter has the capability to retransmit data.
The Powerline Network Protocol also supports an 8-bit CRC
for error detection and data packet retransmission.
A Carrier Sense Multiple Access (CSMA) scheme is built into
the network protocol that minimizes collisions between packet
transmissions on the powerline and supports multiple masters
and reliable communication on a bigger network.
1.2 Powerline Modem PHY
Figure 1-1. Physical Layer FSK Modem
Powerline Communication Solution
Powerline Network
Protocol
Physical Layer FSK
Modem
PLC Core
Embedded Application
Programmable
System Resources
Digital and Analog
Peripherals
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
Powerline Transceiver Packet
The physical layer of the Cypress PLC solution is implemented
using an FSK modem that enables half duplex communication
on any high voltage and low voltage powerline. This modem
supports raw data rates up to 2400 bps. A block diagram is
shown in Figure 1-2.
Figure 1-2. Physical Layer FSK Modem Block Diagram
Network Protocol
Digital
Transmitter
Local
Oscillator
Logic ‘1’ or
Logic ‘0’
Modulator
Square Wave
at FSK
Frequencies
Programmable
Gain Amplifier
Digital
Receiver
Hysteresis
Comparator
Low Pass
Filter
Correlator
IF Band
Pass Filter
Mixer
Local
Oscillator
HF Band
Pass Filter
RX
Amplifier
External Low
Pass Filter
Coupling Circuit
1.2.1 Transmitter Section
Digital data from the network layer is serialized by the digital
transmitter and fed as input to the modulator. The modulator
divides the local oscillator frequency by a definite factor
depending on whether the input data is high level logic ‘1’ or low
level logic ‘0’. It then generates a square wave at 133.3 kHz (logic
‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable
Gain Amplifier to generate FSK modulated signals. This enables
tunable amplification of the signal depending on the noise in the
channel. The logic ‘1’ frequency can also be configured as
130.4 kHz for wider FSK deviation.
1.2.2 Receiver Section
The incoming FSK signal from the powerline is input to a high
frequency (HF) band pass filter that filters out-of-band frequency
components and outputs a filtered signal within the desired
spectrum of 125 kHz to 140 kHz for further demodulation. The
mixer block multiplies the filtered FSK signals with a locally
generated signal to produce heterodyned frequencies.
Document Number: 001-48325 Rev. *E
www.DataSheet.in
Page 2 of 44
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Part Number CY8CPLC20
Description Powerline Communication Solution
Maker Cypress Semiconductor
Total Page 30 Pages
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