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Cypress Semiconductor Electronic Components Datasheet

CY8CPLC10 Datasheet

Powerline Communication Solution

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CY8CPLC10 pdf
CY8CPLC10
Powerline Communication Solution
Features
Integrated Powerline Modem PHY
2400 bps Frequency Shift Keying Modulation
Powerline Optimized Network Protocol
Integrates Data Link, Transport, and Network Layers
Supports Bidirectional Half-Duplex Communication
CRC Error Detection to Minimize Data Loss
I2C enabled Powerline Application Layer
Supports I2C Frequencies of 50, 100, and 400 kHz
Reference Designs for 110V to 240V AC, 12V to 24V AC/DC
Coupling Circuits
Reference Designs Comply with CENELEC EN50065-1:2001
and FCC Part 15
Applications
Residential and commercial lighting control
Home automation
Automatic meter reading
Industrial control and signage
Smart energy management
Logic Block Diagram
Host System
Functional Overview
The CY8CPLC10 is an integrated Powerline Communication
solution with the Powerline Modem PHY and Powerline Network
Protocol Stack on the same chip. This helps in robust communi-
cation between different nodes on a Powerline.
Powerline Transmitter
The application residing on a host microcontroller generates
messages to be transmitted on the Powerline. These messages
are delivered to the CY8CPLC10 over an I2C serial link.
The Powerline Network Layer residing on the CY8CPLC10
receives these I2C messages and generates a Powerline Trans-
ceiver (PLT) packet. These packets are modulated by the FSK
Modem and coupled with Powerline by the external coupling
circuit.
Powerline Receiver
Powerline signals are received by the coupling circuit and
demodulated by the FSK Modem PHY. These PLT packets are
decoded by the Powerline Network Protocol and then transferred
to the external host microcontroller in an I2C format.
Powerline Communication Solution
PSoCTM/
External µC
I2C Packet
Powerline Network
Protocol
Application
Circuitry
Powerline
FSK Modem
PHY
AC/DC Powerline
Coupling Circuit
(110V-240V AC, 12V-24V
AC/DC, etc.)
Powerline
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-50001 Rev *C
www.DataSheet.in
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 21, 2009
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Cypress Semiconductor Electronic Components Datasheet

CY8CPLC10 Datasheet

Powerline Communication Solution

No Preview Available !

CY8CPLC10 pdf
CY8CPLC10
Robust Communication using Cypress’s
PLC Solution
Powerlines are one of the world’s most widely available commu-
nication mediums for PLC technology. The pervasiveness of
Powerlines also makes it difficult to predict the characteristics
and operation of PLC products. Because of the variable quality
of Powerline around the world, implementing robust communi-
cation over Powerline is an engineering challenge. Keeping this
in mind, Cypress's PLC solution is designed to enable secure
and reliable communication over Powerline. Cypress PLC
features that enable robust communication over Powerline
include:
Integrated Powerline PHY modem with optimized filters and
amplifiers to work with lossy high voltage and low voltage
Powerlines.
Powerline optimized Network Protocol that supports bidirec-
tional communication with acknowledgement based signaling.
In case of data packet loss due to bursty noise on the Powerline,
the transmitter can retransmit data.
The Powerline Network Protocol also supports 8-bit CRC for
error detection and data packet retransmission.
A Carrier Sense Multiple Access (CSMA) scheme, built into the
Network Protocol, minimizes collisions between packet trans-
missions on the Powerline. This provides support for multiple
masters and reliable communication on a bigger network.
Detailed Description
Figure 1. CY8CPLC10 Internal Block Diagram
CLKSEL
External External
Clock Crystal
INT
TX RX BIU
SCL
SDA
Clocking
Circuitry
Status and interrupt signals
TX
Buffer
FSK
Modulator
FSK Out
I2C
Interface
Memory
Array
Processor
RX
Buffer
FSK
De-Modulator
FSK In
EEPROM
I2C Address
Select
3-bit Logical
Address
The CY8CPLC10 consists of two main functional components:
Powerline Modem PHY
Powerline Network Protocol
The application resides on a host system such as PSoC®,
EZ-Color, or any other microcontroller. The messages
generated by the application are communicated to the
CY8CPLC10 over I2C and processed by these functional
components. The following sections present a brief description
of each of these components.
Powerline Modem PHY
Figure 2. CY8CPLC10: FSK Modem PHY
Powerline Communication Solution
I2C Packet
Powerline Network
Protocol
Powerline
FSK Modem
PHY
The physical layer of Cypress’s PLC solution is implemented
using an FSK modem that enables half duplex communication
on a Powerline. This modem supports raw data rates up to 2400
bps.
Figure 3. CY8CPLC10: FSK Modem PHY Block Diagram
Network Protocol
Digital
Transmitter
Local
Oscillator
Logic ‘1’ or
Logic ‘0’
Modulator
Square Wave
at FSK
Frequencies
Programmable
Gain Amplifier
Digital
Receiver
Hysteresis
Comparator
Low Pass
Filter
Correlator
IF Band
Pass Filter
Mixer
Local
Oscillator
HF Band
Pass Filter
RX
Amplifier
Automatic
Gain Control
External Low
Pass Filter
Coupling Circuit
Document Number: 001-50001 Rev. *D
www.DataSheet.in
Page 2 of 25
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Part Number CY8CPLC10
Description Powerline Communication Solution
Maker Cypress Semiconductor
Total Page 25 Pages
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