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Cypress Semiconductor Electronic Components Datasheet

CY8C9520 Datasheet

(CY8C9520 - CY8C9560) I/O Expander

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CY8C9520 pdf
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Cypress Semiconductor
CY8C9520,
CY8C9540, and CY8C9560
Preliminary Data Sheet
20-, 40-, and 60-Bit I/O Expander with EEPROM
Features
I2C™ interface logic electrically compatible with SMBus.
Up to 20 (CY8C9520), 40 (CY8C9540) or 60 (CY8C9560)
I/O data pins independently configurable as inputs, outputs,
bi-directional input/outputs or PWM outputs.
4/8/16 PWM sources with 8-bit resolution.
Extendable Soft Addressing™ algorithm allowing flexible
I2C-address configuration.
Internal 3-/11-/27-Kbyte EEPROM.
Storage of user defaults and I/O port settings in the internal
EEPROM.
Optional EEPROM Write Disable (WD) input.
Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes.
Internal power-on reset (POR).
WD EEPROM
User
Settings
Area
User
A vailable
Area
Clocks
32 kHz
24 MHz
1.5 MHz
93.75 kHz
Divider (1-255)
PWM 0
PWM 15
Control
Unit
GPort 0
GPort 1
GPort 2
8 Bit I/O
5 Bit I/O
3 Bit I/O
or A4-A6
4 Bit I/O
or A1-A3, W
GPort 3
8 Bit I/O
GPort 7
8 Bit I/O
SCL
SDA
Vdd
Vss
Pow er-on-Reset
INT
A0
Overview
The CY8C95xx is a multi-port I/O expander with on-board user-
available EEPROM and several PWM outputs. All devices in
this family operate identically but differ in I/O pins, number of
PWMs, and internal EEPROM size.
The CY8C95xx operates as two I2C slave devices. The first
device is a multi-port I/O expander (single I2C address to
access all ports via registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to dis-
able the EEPROM. The EEPROM utilizes 2-byte addressing to
support the 28-Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM
ouputs. The individual data pins can be configured as open
drain/collector, strong drive (10 mA source, 25 mA sink), resis-
tively pulled-up/-down, or high-impedance. The factory default
configuration is pulled-up internally.
The system master writes to the I/O configuration registers via
the I2C bus. Configuration and output register settings can be
stored as user defaults in a dedicated section of the EEPROM.
If user defaults have been stored in EEPROM, they are
restored to the ports at power-up. While this device can share
the bus with SMBus devices, it can only communicate with
I2C-masters.
There is one dedicated pin that is configured as an interrupt out-
put (INT) and can be connected to the interrupt logic of the sys-
tem master. This signal can inform the system master that there
is incoming data on its ports or that the PWM output state was
changed.
The EEPROM is byte-readable and supports byte-by-byte writ-
ing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The con-
figuration registers can also disable EEPROM operations.
The CY8C95xx has one fixed address pin (A0) and up to six
additional pins (A1-A6) which allow up to 128 devices to share a
common two-wire I2C data bus. The Extendable Soft Address-
ing algorithm provides the option to choose the number of pins
needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
Figure 1-1. Top Level Block Diagram
August 17, 2005
© Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A
1


Cypress Semiconductor Electronic Components Datasheet

CY8C9520 Datasheet

(CY8C9520 - CY8C9560) I/O Expander

No Preview Available !

CY8C9520 pdf
www.DataSheet4U.com
CY8C95xx Preliminary Data Sheet
Overview
There are 4 (CY8C9520), 8 (CY8C9540) or 16 (CY8C9560)
independently configurable 8-bit PWMs. These PWMs are
denoted as PWM0-PWM15. Each PWM can be clocked by one
of six available clock sources.
Architecture
The figure titled “Top Level Block Diagram” on page 1 illustrates
the device block diagram. The main blocks include the control
unit, PWMs, EEPROM and I/O ports. The control unit executes
commands received from the I2C bus and transfers data
between other bus devices and the master device.
The on-chip EEPROM can be separated conventionally into two
regions. The first region is designed to store data and is avail-
able for byte-wide read/writes via the I2C bus. It is possible to
prevent write operations by setting the WD pin to high. All
EEPROM operations can be blocked by configuration register
settings. The second region allows the user to store the port
and PWM default settings using special commands. These
defaults will be automatically reloaded and processed after
device power-on.
The number of I/O lines and PWM sources is presented in the
following table.
Data
PWMs
7 Drive Mode
Registers
DriveMode
Pull-Up
DriveMode
High-Z
Interrupt
Status
Interrupt
Mask
Pin Direction
GPortx
Output
Register
Select PWM
Input Register
8 Bit I/O
Inversion
Table 1-1. GPIO Availability
Port
CY8C9520
CY8C9540
CY8C9560
GPort 0
8 bit 8 bit 8 bit
GPort 1
5-8 bit
5-8bit
5-8 bit
GPort 2
0-4 bit
0-4bit
0-4 bit
GPort 3
- 8 bit 8 bit
GPort 4
- 8 bit 8 bit
GPort 5
- 4 bit 8 bit
GPort 6
- - 8 bit
GPort 7
- - 8 bit
PWMs
4 8 16
* This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.
There are four pins on GPort 2 and three on GPort 1 that can be
used as general purpose I/O or EEPROM Write Disable (WD)
and I2C-address input (A1-A6), depending on configuration set-
tings.
The figure titled “Logical Structure of the I/O Port” shows the
single port logical structure. The Port Drive Mode register gives
the option to select one of seven available modes for each pin
separately: pulled-up/-down, open drain high/low, strong drive
fast/slow, or high-impedance. By default these configuration
registers store values setting I/O pins to pulled-up. The Invert
register allows for inversion of the logic of the Input registers
separately for each pin. The Select PWM register allows pins to
be assigned as PWM outputs. All of these configuration regis-
ters are read/writable using corresponding commands in the
multi-port device.
Figure 1-2. Logical Structure of the I/O Port
The Port Input and Output registers are separated. When the
Output register is written, the data is sent to the external pins.
When the Input register is read, the external pin logic levels are
captured and transferred. As a result, the read data can be dif-
ferent from written Output register data. This allows for imple-
mentation of a quasi-bidirectional input-output mode, when the
corresponding binary digit is configured as pulled-up/down out-
put.
Each GPort has an Interrupt Mask register and an Interrupt Sta-
tus register. Each high bit in the Interrupt Status register signals
that there has been a change in the corresponding input line
since the last read of that Interrupt Status register. The Interrupt
Status register is cleared after each read. The Interrupt Mask
register enables/disables activation of the INT line when input
levels are changed. Each high in the Interrupt Mask register
masks (disables) an interrupt generated from the corresponding
input line.
Applications
Each GPIO pin can be used to monitor and control various
board-level devices, including LEDs and system intrusion
detection devices.
The on-board EEPROM can be used to store information such
as error codes or board manufacturing data for read-back by
application software for diagnostic purposes.
August 17, 2005
Document No. 38-12036 Rev. *A
2


Part Number CY8C9520
Description (CY8C9520 - CY8C9560) I/O Expander
Maker Cypress Semiconductor
Total Page 25 Pages
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