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Cypress Semiconductor Electronic Components Datasheet

CY2304 Datasheet

3.3V Zero Delay Buffer

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CY2304 pdf
CY2304
3.3V Zero Delay Buffer
Features
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multiple configurations – see “Available Configura-
tions” table
• Multiple low-skew outputs
— Output-output skew less than 200 ps
— Device-device skew less than 500 ps
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25 µA of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the Available Configurationstable. The CY23041
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY23042 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin.
Logic Block Diagram
REF
PLL
FBK
CLKA1
CLKA2
/2 Extra Divider (-2)
CLKB1
Pin Configuration
8-pin SOIC
Top View
REF
CLKA1
CLKA2
GND
1
2
3
4
8 FBK
7 VDD
6 CLKB2
5 CLKB1
CLKB2
Available Configurations
Device
FBK from
CY2304-1
Bank A or B
CY2304-2
Bank A
CY2304-2
Bank B
Bank A Frequency Bank B Frequency
Reference
Reference
Reference
Reference/2
2 × Reference
Reference
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07247 Rev. *C
Revised December 7, 2002


Cypress Semiconductor Electronic Components Datasheet

CY2304 Datasheet

3.3V Zero Delay Buffer

No Preview Available !

CY2304 pdf
Pin Description
Pin Signal
1 REF[1]
2 CLKA1[2]
3 CLKA2[2]
4 GND
5 CLKB1[2]
6 CLKB2[2]
7 VDD
8 FBK
Description
Input reference frequency, 5V-tolerant input
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3V supply
PLL feedback input
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins
CY2304
To close the feedback loop of the CY2304, the FBK pin can be
driven from any of the four available output pins. The output
driving the FBK pin will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2304, refer to the appli-
cation note CY2308: Zero Delay Buffer.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
Document #: 38-07247 Rev. *C
Page 2 of 8


Part Number CY2304
Description 3.3V Zero Delay Buffer
Maker Cypress Semiconductor
Total Page 8 Pages
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