Figure 1. Pin Configuration – 8-Pin SOIC Package
Table 2. Pin Definition
Pin Name Pin No
Reference Input: The output signals are synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback is
equal in length to the traces between the outputs and the signal destinations, then the signals
received at the destinations are synchronized to the REF signal input (IN).
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table 1.
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-F
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
Ground Connection: Connect all grounds to the common system ground plane.
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
Document #: 38-07154 Rev. *E
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