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Cypress Semiconductor Electronic Components Datasheet

CY2273A Datasheet

K6 Clock Synthesizer/Driver

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CY2273A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs
with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium®, Pentium® II,
Cyrix, and AMD processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to twelve 3.3V SDRAM clocks
— Seven synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 2.5V IOAPIC clock (-3 option only)
— Two AGP clocks at 60 or 66.6MHz (-2 option only)
— One 3.3V Ref. clock at 14.318 MHz
• I2C™ Serial Configuration Interface
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Power-down, CPU stop and PCI stop pins
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2273A is a clock synthesizer/driver for a Pentium, Pen-
tium II, Cyrix, or AMD processor-based PC using Intel’s
82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.
The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with
up to 83.3MHz operation. There are seven PCI clocks, running
at 30 and 33.3MHz. One of the PCI clocks is free-running.
Additionally, the part outputs up to twelve 3.3V SDRAM clocks,
one 3.3V USB clock at 48 MHz, and one 3.3V reference clock
at 14.318 MHz. The CY2273A-2 is similar, except that
PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3
is more suited to Pentium II systems, as it outputs one 2.5V
IOAPIC clock. Finally, the CY2273A-4 is similar to the
CY2273A-1 except that is supports 0-ns CPU-PCI delay.
The CY2273A possesses power-down, CPU stop, and PCI
stop pins for power management control. These inputs are
multiplexed with SDRAM clock outputs, and are selected when
the MODE pin is driven low. Additionally, the signals are syn-
chronized on-chip, and ensure glitch-free transitions on the
outputs. When the CPU_STOP input is asserted, the CPU
clock outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all out-
puts are driven LOW.
The CY2273A outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2273A Selector Guide
Clocks Outputs
-1
-2 -3 -4
CPU (60, 66.6, 75,
83.3 MHz)
CPU (60, 66.6 MHz)
4
--
4 -- 4
-- 4 --
SDRAM
PCI (30, 33.3MHz)
9/12
7[1]
9/12
5[1]
9/12
7[1]
9/12
7[1]
USB/IR (48MHz)
1 1 11
AGP (60 or 66MHz)
--
2 -- --
IOAPIC (14.318MHz)
--
-- 1 --
Ref (14.318MHz)
1 1 11
CPU-PCI delay
1–5.5 ns 1–5.5 ns
Note:
1. One free-running PCI clock.
0 ns
0 ns
Logic Block Diagram
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
STOP
LOGIC
CY2273A-3 only
IOAPIC
VDDQ2
REF0 (14.318 MHz)
CPUCLK [0-3]
VDDCPU
SEL0
SEL1
CY2273A-1,-2,-4 only
MODE
EPROM
SDRAM5/PWR_DWN
SDRAM [0-4],[8-11]
SDRAM6/CPU_STOP
Delay (-1,-2 option)
SYS PLL
SDRAM7/PCI_STOP
/1 or /1.25
/1 or /2
STOP
LOGIC
CY2273A-2 only
AGP [0,1]
PCI [0-5], PCI [0-3]
SCLK
SDATA
SERIAL
INTERFACE
CONTROL
LOGIC
PCICLK_F
USBCLK (48 MHz)
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134
• 408-943-2600
October 12, 1998



Cypress Semiconductor Electronic Components Datasheet

CY2273A Datasheet

K6 Clock Synthesizer/Driver

No Preview Available !

CY2273A pdf
CY2273A
Pin Configurations
CY2273A-1,-4
SSOP
Top View
AVDD
REF0
VSS
XTALIN
XTALOUT
VDDQ3
PCICLK_F
PCICLK0
VSS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDQ3
PCICLK5
VSS
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ3
47 USBCLK
46 SEL1
45 VSS
44 CPUCLK0
43 CPUCLK1
42 VDDCPU
41 CPUCLK2
40 CPUCLK3
39 VSS
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 VSS
32 SDRAM4
31 SDRAM5/PWR_DWN
30 VDDQ3
29 SDRAM6/CPU_STOP
28 SDRAM7/PCI_STOP
27 VSS
26 SEL0
25 MODE
CY2273A-2
SSOP
Top View
CY2273A-3
SSOP
Top View
AVDD
REF0
VSS
XTALIN
XTALOUT
VDDQ3
PCICLK_F
PCICLK0
VSS
PCICLK1
PCICLK2
PCICLK3
AGP0
VDDQ3
AGP1
VSS
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ3
47 USBCLK
USBCLK
REF0
1
2
46 SEL1
45 VSS
44 CPUCLK0
43 CPUCLK1
VSS
XTALIN
XTALOUT
VDDQ3
3
4
5
6
42 VDDCPU
PCICLK_F 7
41 CPUCLK2
40 CPUCLK3
PCICLK0
VSS
8
9
39 VSS
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDQ3
10
11
12
13
14
34 SDRAM3
PCICLK5 15
33 VSS
VSS 16
32 SDRAM4
SDRAM11 17
31 SDRAM5/PWR_DWN SDRAM10 18
30 VDDQ3
VDDQ3 19
29 SDRAM6/CPU_STOP SDRAM9 20
28 SDRAM7/PCI_STOP
27 VSS
26 SEL0
SDRAM8
VSS
AVDD
21
22
23
25 MODE
SDATA 24
48 VDDQ2
47 IOAPIC
46 SEL0
45 VSS
44 CPUCLK0
43 CPUCLK1
42 VDDCPU
41 CPUCLK2
40 CPUCLK3
39 VSS
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 VSS
32 SDRAM4
31 SDRAM5/PWR_DWN
30 VDDQ3
29 SDRAM6/CPU_STOP
28 SDRAM7/PCI_STOP
27 VSS
26 MODE
25 SCLK
2



Cypress Semiconductor Electronic Components Datasheet

CY2273A Datasheet

K6 Clock Synthesizer/Driver

No Preview Available !

CY2273A pdf
CY2273A
Pin Summary
Name
Pins (-1, -4)
Pins (-2)
Pins (-3)
Description
VDDQ3
6, 14, 19, 30, 36, 6, 14, 19, 30, 36, 6, 14, 19, 30, 36 3.3V Digital voltage supply
48 48
VDDQ2
VDDCPU
AVDD
VSS
XTALIN[2]
XTALOUT[2]
N/A
42
1
3, 9, 16, 22, 27,
33, 39, 45
4
5
N/A
42
1
3, 9, 16, 22, 27,
33, 39, 45
4
5
48
42
23
3, 9, 16, 22, 27,
33, 39, 45
4
5
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V or 3.3V
Analog voltage supply, 3.3V
Ground
Reference crystal input
Reference crystal feedback
SDRAM7/
28
28
28
SDRAM clock output. Also, active low control input
PCI_STOP
to stop PCI clocks, enabled when MODE is LOW.
SDRAM6/
29
29
29
SDRAM clock output. Also, active low control input
CPU_STOP
to stop CPU clocks, enabled when MODE is LOW.
SDRAM5/
31
31
31
SDRAM clock output. Also, active low control input
PWR_DWN
to power down device, enabled when MODE is LOW.
SDRAM[0:4], 38, 37, 35, 34, 38, 37, 35, 34, 38, 37, 35, 34, SDRAM clock outputs
[8:11]
32, 21, 20, 18, 17 32, 21, 20, 18, 17 32, 21, 20, 18, 17
SEL0
26
26
46
CPU frequency select input, bit 0 (See table below.)
SEL1
46
46
N/A CPU frequency select input, bit 0 (See table below.)
CPUCLK[0:3] 44, 43, 41, 40 44, 43, 41, 40 44, 43, 41, 40 CPU clock outputs
PCICLK[0:5] or 8, 10, 11, 12, 13, 8, 10, 11, 12
PCICLK[0:3] 15
8, 10, 11, 12, 13, PCI clock outputs, at 30 or 33.33 MHz
15
PCICLK_F
7
7
7
Free-running PCI clock output
AGPCLK[0:1] N/A
13, 15
N/A
AGP clock outputs at 60 or 66.66 MHz
IOAPIC
N/A
N/A
47
IOAPIC clock output
REF0
2
2
2
3.3V Reference clock output
USBCLK
47
47
1
USB Clock output at 48 MHz
SDATA
23
23
24
Serial data input for serial configuration port
SCLK
24
24
25
Serial clock input for serial configuration port
MODE
25
25
26
Mode Select pin for enabling power management
features
Note:
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Function Table (-1, -2 and -4)
CPU/PCI
SEL1 SEL0
Ratio
002
012
1 0 2.5
1 1 2.5
CPUCLK[0:3]
SDRAM[0:11]
60.0 MHz
66.67 MHz
75.0 MHz
83.33 MHz
PCICLK[0:5]
PCICLK_F
30.0 MHz
33.33 MHz
30.0 MHz
33.33 MHz
AGP
(-2 Only)
60.0 MHz
66.66 MHz
60.0 MHz
66.66 MHz
REF0
IOAPIC
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
USBCLK
48 MHz
48 MHz
48 MHz
48 MHz
Function Table (-3)
SEL0
0
1
CPU/PCI Ratio
2
2
CPUCLK[0:3]/SDRAM[0:11]
60.0 MHz
66.67 MHz
PCICLK[0:5],PCICLK_F
30.0 MHz
33.33 MHz
REF0/IOAPIC
14.318 MHz
14.318 MHz
USBCLK
48 MHz
48 MHz
3




Part Number CY2273A
Description K6 Clock Synthesizer/Driver
Maker Cypress Semiconductor
Total Page 14 Pages
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