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Cypress Semiconductor Electronic Components Datasheet

CY2081 Datasheet

Three-PLL General-Purpose EPROM-Programmable Clock Generator

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CY2081
Three-PLL General-Purpose
EPROM-Programmable Clock Generator
Features
Factory-EPROM configurable for quick availability and
prototyping
General purpose clock synthesizer for all applications
– such as modems, disk drives, CD-ROM drives, Video
CD players, games, set-top boxes, data/telecommuni-
cations, etc.
Three independent configurable clock outputs
Outputs ranging from 500 kHz to 100 MHz (5V) and up
to 80 MHz for 3.3V operation
Configurable output control pin (pin 8) can be used as
an output enable, power-down, suspend or select line.
Phase-locked loop oscillator input derived from exter-
nal crystal (10 MHz to 25 MHz) or external reference
clock (1 MHz to 30 MHz)
3.3V or 5V operation (factory configured)
8-pin 150-mil packaging achieves minimum footprint
for space-critical applications
Sophisticated internal loop filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
Functional Description
The CY2081 is a general-purpose clock synthesizer designed
for use in applications such as modems, disk drives, CD-ROM
drives, Video CD players, games, set-top boxes and data/tele-
communications. This devices offers three configurable clock
outputs in an 8-pin 150-mil SOIC package and can be config-
ured to operate off either a 3.3V or 5V power supply. The
on-chip reference oscillator is designed for 10 MHz to 25 MHz
crystals. Alternatively, a reference clock between 1 MHz and
30 MHz can be used.
The CY2081 also features an output control pin (pin 8), which
can be configured as an output enable, power down, frequen-
cy select, or suspend input. This gives the user the ability to
three-state the output, power down the device, change the
CLKA output frequency during operation, or suspend any of
the outputs. Asserting the PD input will result in all the PLLs
and the outputs being shut down. The PLLs will have to re-lock
when the PD input is deasserted.
The CY2081 outputs three clocks: CLKA, CLKB, and CLKC,
whose frequencies can possess any value within the specified
range. Additionally, the reference frequency can be obtained
on any output. Custom configurations with user-defined fea-
tures and frequencies can be obtained by filling out the custom
configuration form located at the back of this data sheet and
contacting your local Cypress representative.
The CY2081 can replace multiple Metal Can Oscillators
(MCO) in a synchronous system, providing cost and board
space savings to manufacturers. Hence, this device is ideally
suited for applications that require multiple, accurate, and sta-
ble clocks synthesized from low-cost generators in small pack-
ages. A hard disk drive is an example of such an application.
In this case, CLKA drives the PLL in the Read Controller, while
CLKB and CLKC drive the MCU and associated sequencers.
Consider using the CY2291, CY2292, or CY2907 for applica-
tions that require more than three output clocks.
Logic Block Diagram
Pin Configuration
SOIC
Top View
CLKA
GND
XTALIN
XTALOUT
1
2
3
4
8 OE/PD/FS/SUSPEND
7 VDD
6 CLKC
5 CLKB
XTALIN
XTALOUT
Reference
Oscillator
PLL 1
PLL 2
PLL 3
EPROM-
Configurable
Multiplexer
and Divide
Logic
CLKA
CLKB
CLKC
OE/PD/FS/SUSPEND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07136 Rev. **
Revised September 26, 2001



Cypress Semiconductor Electronic Components Datasheet

CY2081 Datasheet

Three-PLL General-Purpose EPROM-Programmable Clock Generator

No Preview Available !

CY2081 pdf
CY2081
Pin Summary
Name
Number
CLKA
1
GND
XTALIN[1]
XTALOUT[1,2]
2
3
4
CLKB
5
CLKC
6
VDD
7
OE / PD / FS / SUSPEND 8
Description
Configurable Clock Output
Ground
Reference Crystal Input or External Reference Clock Input
Reference Crystal Feedback
Configurable Clock Output
Configurable Clock Output
Voltage Supply
Output control pin; either active-HIGH Output Enable, active-LOW power down, CLKA
Frequency Select, or active-LOW Suspend input
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ............................................... 0.5V to +7.0V
DC Input Voltage......................................0.5V to VDD+0.5V
Storage Temperature ................................. 65°C to +150°C
Junction Temperature...................................................150°C
Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015)
Operating Conditions[3]
Parameter
Description
VDD Supply Voltage
TA Operating Temperature, Ambient
CL Max. Load Capacitance per output
fREF External Reference Crystal
fREF
External Reference Clock[4, 5]
Min.
4.5 (3.0)
0
10.0
1.0
Max.
5.5 (3.6)
70
25 (15)
25.0
30.0
Unit
V
°C
pF
MHz
MHz
Electrical Characteristics VDD = 5V (3.3V) ±10%, TA = 0°C to +70°C
Parameter
Description
Conditions
Min.
Typ.
VOH HIGH-Level Output Voltage IOH = 4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
VIH HIGH-Level Input Voltage[6] Except Crystal Pins
VIL LOW-Level Output Voltage[6] Except Crystal Pins
2.0
IIH Input HIGH Current
VIN = VDD 0.5V
<100
IIL Input LOW Current
VIN = 0.5V
<100
IOZ
Output Leakage Current
Three State Outputs
IDD VDD Supply Current[7] VDD = VDD max. 5V (3.3V) operation, CL
= 25 pF (15 pF)
40 (24)
IDDS
VDD Power Supply Current in Power-down Active, 5V Operation
Power-down Mode
100
Notes:
1. For best accuracy, use a parallel-resonant crystal, CL=17 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal).
3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses.
4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
5. Please refer to application note Crystal Oscillator Topicsfor information on AC-coupling the external input reference clock.
6. Xtal inputs have CMOS thresholds.
7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary.
Max.
0.4
0.8
150
150
250
60 (40)
200
Unit
V
V
V
V
µA
µA
µA
mA
µA
Document #: 38-07136 Rev. **
Page 2 of 6



Cypress Semiconductor Electronic Components Datasheet

CY2081 Datasheet

Three-PLL General-Purpose EPROM-Programmable Clock Generator

No Preview Available !

CY2081 pdf
CY2081
Switching Characteristics[8]
Parameter
Name
t1 Output Period
Description
Clock output range, 5V operation
t1
Output Period
Clock output range, 3.3V operation
t1A Clock Jitter[9] Peak-to-peak period jitter,% of clock period
(fOUT 4 MHz)
t1B Clock Jitter[9] Peak-to-peak period jitter
(4 MHz fOUT 16 MHz)
t1C Clock Jitter[9] Peak-to-peak period jitter
(16 MHz < fOUT 50 MHz)
t1D Clock Jitter[9] Peak-to-peak period jitter
(fOUT > 50 MHz)
Output Duty Cycle[10] Duty cycle for outputs, defined as t2 ÷ t1[11]
fOUT > 66.67 MHz
Duty cycle for outputs, defined as t2 ÷ t1[11]
fOUT 66.67 MHz
t3 Rise time
Output clock rise time[12] at CL=25 pF (15 pF
at 3.3V operation)
t4 Fall time
Output clock fall time[12] at CL=25 pF (15 pF
at 3.3V operation)
t5 Frequency Slew Rate Rate of change of frequency of CLKA
Min.
10
[100 MHz]
12.5
[80 MHz]
40%
45%
1
t6 Power Up Stabiliza- Output clock stable time after power up
tion Time
Typ.
<0.5
<0.7
<400
<250
50%
50%
3
2.5
5
< 25
Max.
2000
[500 KHz]
2000
[500 KHz]
1
1
500
350
60%
55%
5
4
40
50
Unit
ns
ns
%
ns
ps
ps
ns
ns
MHz/
ms
ms
Switching Waveforms
All Outputs Duty Cycle and Rise/Fall Time
OUTPUT
2.4V
0.4V
t3
t2
t1
2.4V
0.4V
t4
3.3V
0V
Notes:
8. Guaranteed by design, not 100% tested.
9. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to
the application note: Jitter in PLL-Based Systems.
10. Reference Output duty cycle depends on XTALIN duty cycle.
11. Measured at 1.4V.
12. Measured between 0.4V and 2.4V.
Document #: 38-07136 Rev. **
Page 3 of 6




Part Number CY2081
Description Three-PLL General-Purpose EPROM-Programmable Clock Generator
Maker Cypress Semiconductor
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