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Cypress Semiconductor Electronic Components Datasheet

C9827H Datasheet

High Performance Pentium 4 Clock Synthesizer

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C9827H pdf
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Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Product Features
Supports Pentium® 4 Type CPUs
3.3 Volt Power Supply
10 Copies of PCI Clocks
3 Differential CPU Clocks
SMBus Support with Read-back Capabilities
Spread Spectrum EMI Reduction
Dial-a-Frequency™ Features
Dial-a-dB™ Features
56 Pin SSOP and TSSOP Package
Frequency Table
S2 S1 S0 CPU
3V66 66BUFF(0:2)/
66IN/
PCI_F
REF
(0:2)
3V66(0:4)
3V66-5
PCI
1 0 0 66M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 0 1 100M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 1 0 200M
66M
66IN
66MHz clock input 66IN/2 14.318M
1 1 1 133M
66M
66IN
66MHZ clock input 66IN/2 14.318M
0 0 0 66M
66M
66M
66M
33 M
14.318M
0 0 1 100M
66M
66M
66M
33 M
14.318M
0 1 0 200M
66M
66M
66M
33 M
14.318M
0 1 1 133M
66M
66M
66M
33 M
14.318M
M 0 0 Hi-Z
Hi-Z
Hi-Z
Hi-Z Hi-Z Hi-Z
M 0 1 TCLK/2 TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
M 1 0 150M
50M
50M
50M 25M 14.318M
M 1 1 166.6M 55.5M
55.5M
55.5M
27.7M 14.318M
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
48M
48M
Block Diagram
Pin Configuration
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PD#
SDATA
SCLK
VDDA
PLL2
WD
Logic
I2C
Logic
Power
Up Logic
REF
CPU(0:2)
CPU/(0:2)
3V66_0
3V66_1/VCH
/2 PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
66B[0:2]/3V66[2:4]
66IN/3V66-5
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF
55 S1
54 S0
53 CPU_STP#
52 CPU0
51 CPU/0
50 VDD
49 CPU1
48 CPU/1
47 VSS
46 VDD
45 CPU2
44 CPU/2
43 MULT0
42 IREF
41 VSSIREF
40 S2
39 48MUSB
38 48MDOT
37 VDD
36 VSS
35 3V66_1/VCH
34 PCI_STP#
33 3V66_0
32 VDD
31 VSS
30 SCLK
29 SDATA
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 1 of 25


Cypress Semiconductor Electronic Components Datasheet

C9827H Datasheet

High Performance Pentium 4 Clock Synthesizer

No Preview Available !

C9827H pdf
Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Pin Description
PIN
NAME
PWR I/O
Description
2 XIN
I Oscillator Buffer Input. Connect to a crystal or to an external clock.
3
XOUT
VDD
O Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
52, 51, 49, CPU, CPU/
VDD
O Differential host output clock pairs. See the frequency table on page
48, 45, 44
(0:2)
one of this data sheet for frequencies and functionality.
10, 11, 12, PCI(0:6)
VDDP O PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See
13, 16, 17, 18
Frequency Table on page one of this data sheet.
5, 6, 7
PCIF (0:2)
VDD
O 33Mhz PCI clocks, which are ÷2 copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of SMBus register Byte3,
Bits (3:5).
56
REF
VDD
O Buffered Output copy of the device’s XIN clock.
42
IREF
VDD
I Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current
Select Table in page 18 of this data sheet.
28
VTT_PG#
VDD
I Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
39
48MUSB
VDD48 O Fixed 48MHz USB Clock Outputs.
38
48MDOT
VDD48 O Fixed 48MHZ DOT Clock Outputs.
33
3V66_0
VDD
O 3.3 Volt 66 MHz fixed frequency clock.
35
3V66_1/VCH VDD
O 3.3 volt clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock.
When byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
25
PD#
VDD
I This pin is a power down mode pin. A logic low level causes the device
PU to enter a power down state. All internal logic is turned off except for the
SMBus logic. All output buffers are stopped. See the Power Down
section of this data sheet.
43 MULT0
I Programming input selection for CPU clock current multiplier. See CPU
PU Clock Current Select Function Table.
55, 54
S(0,1)
I I Frequency Select Inputs. See Frequency Table on page 1.
29
SDATA
I I Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an
open drain output when acknowledging or transmitting data. See
application note AN-0022
30 SCLK I I Serial Clock Input. Conforms to the SMBus specification. See
application note AN-0022.
40 S2
VDD
I Frequency Select input. See Frequency Table on page 1. This is a Tri
T level input that is driven high, low or driven to a intermediate level.
34
PCI_STP#
VDD
I PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
PU synchronously disabled in a low state. This pin does not effect PCIF
(0:2) clocks’ outputs if they are programmed to be PCIF clocks via the
device’s SMBus interface.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 2 of 25


Part Number C9827H
Description High Performance Pentium 4 Clock Synthesizer
Maker Cypress Semiconductor
Total Page 25 Pages
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