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Cypress Semiconductor Electronic Components Datasheet

CY15B256Q Datasheet

256-Kbit (32K x 8) Automotive Serial (SPI) F-RAM

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CY15B256Q pdf
CY15B256Q
256-Kbit (32K × 8) Automotive Serial (SPI)
F-RAM
256-Kbit (32K × 8) Automotive Serial (SPI) F-RAM
Features
Functional Description
256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32K × 8
High-endurance 100 trillion (1014) read/writes
151-year data retention (See the Data Retention and
Endurance table)
NoDelay™ writes
Advanced high-reliability ferroelectric process
Very fast serial peripheral interface (SPI)
Up to 40-MHz frequency
Direct hardware replacement for serial flash and EEPROM
Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
Sophisticated write-protection scheme
Hardware protection using the Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Device ID
Manufacturer ID and Product ID
Low power consumption
2.5-mA active current at 40 MHz
150-A standby current
8-A sleep mode current
Low-voltage operation: VDD = 2.0 V to 3.6 V
Automotive-A temperature: –40 C to +85 C
8-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
The CY15B256Q is a 256-Kbit nonvolatile memory employing an
advanced ferroelectric process. An F-RAM is nonvolatile and
performs reads and writes similar to a RAM. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by serial
flash, EEPROM, and other nonvolatile memories.
Unlike serial flash and EEPROM, the CY15B256Q performs
write operations at bus speed. No write delays are incurred. Data
is written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The CY15B256Q is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the CY15B256Q ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The CY15B256Q provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
CY15B256Q uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
incorporates a read-only Device ID that allows the host to
determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
automotive-a range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
WP
CS
HOLD
SCK
Instruction Decoder
Clock Generator
Control Logic
Write Protect
32 K x 8
F-RAM Array
Instruction Register
Address Register
Counter
15
8
SI SO
Data I/O Register
3
Nonvolatile Status
Register
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90867 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 13, 2016



Cypress Semiconductor Electronic Components Datasheet

CY15B256Q Datasheet

256-Kbit (32K x 8) Automotive Serial (SPI) F-RAM

No Preview Available !

CY15B256Q pdf
CY15B256Q
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
Serial Peripheral Interface - SPI Bus .............................. 4
SPI Overview ............................................................... 4
SPI Modes ................................................................... 5
Power Up to First Access ............................................ 6
Command Structure .................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch ............................... 6
Status Register and Write Protection ............................. 7
RDSR - Read Status Register ..................................... 7
WRSR - Write Status Register .................................... 7
Memory Operation ............................................................ 8
Write Operation ........................................................... 8
Read Operation ........................................................... 8
Fast Read Operation ................................................... 8
HOLD Pin Operation ................................................. 10
Sleep Mode ............................................................... 10
Device ID ................................................................... 11
Endurance ................................................................. 12
Maximum Ratings ........................................................... 13
Operating Range ............................................................. 13
DC Electrical Characteristics ........................................ 13
Data Retention and Endurance ..................................... 14
Capacitance .................................................................... 14
Thermal Resistance ........................................................ 14
AC Test Conditions ........................................................ 14
AC Switching Characteristics ....................................... 15
Power Cycle Timing ....................................................... 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-90867 Rev. *E
Page 2 of 22



Cypress Semiconductor Electronic Components Datasheet

CY15B256Q Datasheet

256-Kbit (32K x 8) Automotive Serial (SPI) F-RAM

No Preview Available !

CY15B256Q pdf
CY15B256Q
Pinout
Figure 1. 8-pin SOIC Pinout
CS 1
8
SO 2 Top View 7
not to scale
WP 3
6
VSS 4
5
VDD
HOLD
SCK
SI
Pin Definitions
Pin Name
SCK
I/O Type
Input
Description
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 40 MHz and may be interrupted at any time.
CS
SI[1]
SO[1]
WP
HOLD
VSS
VDD
Input
Chip Select. This active LOW input activates the device. When HIGH, the device enters the
low-power standby mode, ignores other inputs, and the output is tristated. When LOW, the device
internally activates the SCK signal. A falling edge on CS must occur before every opcode.
Input
Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifica-
tions.
Output
Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other
times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.
Input
Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN is
set to ‘1’. This is critical because other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided on Status Register and Write
Protection on page 7. This pin must be tied to VDD if not used.
Input
HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another
task. When HOLD is LOW, the current operation is suspended. The device ignores any transition
on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin has a weak internal
pull-up (refer to the RIN spec in DC Electrical Characteristics).
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 001-90867 Rev. *E
Page 3 of 22




Part Number CY15B256Q
Description 256-Kbit (32K x 8) Automotive Serial (SPI) F-RAM
Maker Cypress
Total Page 22 Pages
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