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Analog Devices Semiconductor Electronic Components Datasheet

AD6622 Datasheet

Four-Channel/ 75 MSPS Digital Transmit Signal Processor TSP

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AD6622 pdf
a
FEATURES
Wideband Digital IF Parallel Output
Wideband Digital IF Parallel Input
Allows Cascade of Chips for Additional Channels
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
High-Speed CIC Interpolating Filter
NCO Frequency Translation
Worst Spur Better than 100 dBc
Tuning Resolution Better than 0.02 Hz
Real or Complex Outputs
Digital Summation of Channels
Clipped or Wrapped Overrange
Two’s Complement or Offset Binary Output
Separate 3-Wire Serial Data Input for Each Channel
Microprocessor Control
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
WBCDMA
Wireless Local Loop Base Stations
Phase Array Beam Forming Antennas
Four-Channel, 75 MSPS Digital
Transmit Signal Processor (TSP)
AD6622
FUNCTIONAL BLOCK DIAGRAM
CH A SPORT
RCF
CH B SPORT
RCF
CH C SPORT
RCF
CH D SPORT
RCF
JTAG
CIC
FILTER
CIC
FILTER
CIC
FILTER
CIC
FILTER
NCO
NCO
NCO
NCO
PORT
18
18
PRODUCT DESCRIPTION
The AD6622 comprises four identical digital Transmit Signal
Processors (TSPs) complete with synchronization circuitry and
cascadable wideband channel summation. An external digital-
to-analog converter (DAC) is all that is required to complete a
wide band digital up-converter. On-chip tuners allow the relative
phase and frequency for each RF carrier to be independently
controlled.
Each TSP has three cascaded signal processing elements: a
RAM-programmable Coefficient interpolating Filter (RCF), a
programmable Cascaded Integrator Comb (CIC) interpolating
filter, and a Numerically Controlled Oscillator/tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multichannel wideband transmitters, multiple AD6622s may
be combined using the chip’s cascadable output summation stage.
Each channel provides independent serial data inputs that may
be directly connected to the serial port of DSP chips. User pro-
grammable FIR filters can be used to filter linear inputs.
All control registers and coefficient values are programmed through
a generic microprocessor interface. Two microprocessor bus
modes are supported. All inputs and outputs are LVCMOS
compatible. All outputs are LVCMOS and 5 V TTL compatible.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


Analog Devices Semiconductor Electronic Components Datasheet

AD6622 Datasheet

Four-Channel/ 75 MSPS Digital Transmit Signal Processor TSP

No Preview Available !

AD6622 pdf
AD6622–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
VDD
TAMBIENT
Test
Level
IV
IV
AD6622AS
Min Typ
2.4 3.0
–40 +25
Max
3.3
+70
Unit
V
°C
ELECTRICAL CHARACTERISTICS
Parameter (Conditions)
Temp
Test
Level
AD6622AS
Min Typ
Max
Unit
LOGIC INPUTS (5 V TOLERANT)
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
V
2.0
–0.3
3.0 V CMOS
VDD + 0.3 V
+0.8 V
1 10 µA
1 10 µA
4 pF
LOGIC OUTPUTS
Logic Compatibility
Logic “1” Voltage (IOH = 0.25 mA)
Logic “0” Voltage (IOL = 0.25 mA)
IDD SUPPLY CURRENT
CLK = 60 MHz, 3.3 V1
CLK = GSM Example
CLK = IS-136 Example
CLK = WBCDMA Example
Sleep Mode
Full
Full IV VDD – 0.05 VDD – 0.035
V
Full IV
0.02 0.05 V
Full IV
V
V
V
Full IV
506
5661
mA
2972
mA
2402
mA
2092
mA
0.1 0.5 mA
POWER DISSIPATION
CLK = 60 MHz, 3.3 V1
CLK = GSM Example
CLK = IS-136 Example
CLK = WBCDMA Example
Sleep Mode
Full IV
V
V
V
Full IV
1.77
0.892
0.722
0.6272
0.33
1.87
1.65
W
W
W
W
mW
NOTES
1This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC stages,
maximum switching of input data, and maximum VDD of 3.3 V. In an actual application the power will be less; see the Thermal Management section of the data sheet
for further details.
2GSM interpolation = 120 at 65 MHz, 4 channels active, IS-136 interpolation = 2560 at 62.208 MHz, 4 channels active. WBCDMA interpolation = 64, 4 channels
interleaved at 61.44 MHz.
Specifications subject to change without notice.
–2– REV. 0


Part Number AD6622
Description Four-Channel/ 75 MSPS Digital Transmit Signal Processor TSP
Maker Analog Devices
Total Page 28 Pages
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