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AD6600 Datasheet

Dual Channel/ Gain-Ranging ADC with RSSI

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AD6600 pdf
a
Dual Channel, Gain-Ranging
ADC with RSSI
AD6600
FEATURES
Dual IF Inputs, 70 MHz–250 MHz
Diversity or Two Independent IF Signals
Separate Attenuation Paths
Oversample RF Channels
20 MSPS on a Single Carrier
10 MSPS/Channel in Diversity Mode
Total Signal Range 90+ dB
30 dB from Automatic Gain-Ranging (AGC)
60 dB from A/D Converter
Range >100 dB After Processing Gain
Digital Outputs
11-Bit ADC Word
3-Bit RSSI Word
2؋ Clock, A/B Indicator
Single 5 V Power Supply
Output DVCC 3.3 V or 5 V
775 mW Power Dissipation
APPLICATIONS
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
Wireless Local Loop, Fixed Access
PRODUCT DESCRIPTION
The AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes
two input channels, each with 1 GHz input amplifiers and
30 dB of automatic gain-ranging circuitry. Both channels are
sampled with a 450 MHz track-and-hold followed by an 11-bit,
20 MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con-
trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to
3.3 V or 5 V digital processing chips.
The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS
per channel. In single-channel mode, the full clock rate of
20 MSPS may be applied to a single carrier.
The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro-
cessor. The AD6620 provides 10 dB–25 dB of additional pro-
cessing gain before passing data to a fixed- or floating-point DSP.
Driving the AD6600 is simplified by using the AD6630 differen-
tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.
Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.
Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
NOISE FILTER
0dB, –12dB, –24dB
AIN
ATTEN
AIN
DETECT SET
PEAK RSSI
GAIN
3
RSSI
GAIN
BIN
ATTEN
BIN
0dB, –12dB, –24dB
FLT FLT
630
RESONANT
PORT
+12, +18dB
GAIN
SELECT GAIN
ENCODE
TWO'S
A/D COMPLEMENT
CONVERTER
11
ENCODE
3
RSSI
AB_OUT
D10–D0
RSSI [2:0]
AD6600
TIMING
CLK2؋
REV. 0
A_SEL B_SEL
AVCC GND
ENC ENC
DVCC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


Analog Devices Semiconductor Electronic Components Datasheet

AD6600 Datasheet

Dual Channel/ Gain-Ranging ADC with RSSI

No Preview Available !

AD6600 pdf
AD6600–SPECIFICATIONS
DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40؇C, TMAX = +85؇C unless otherwise noted.)
Parameter
ANALOG INPUTS (AIN, AIN/BIN, BIN)
Differential Analog Input Voltage Range1
Differential Analog Input Resistance2
Differential Analog Input Capacitance
Temp
Full
Full
25°C
Test
Level
V
IV
V
AD6600AST
Min Typ
2.0
160 200
1.5
PEAK DETECTOR (Internal), RSSI
Resolution
RSSI Gain Step
RSSI Hysteresis3
RESONANT PORT (FLT, FLT)
Differential Port Resistance
Differential Port Capacitance
Full V
Full V
Full V
Full V
3
6
6
630
1.75
A/D CONVERTER
Resolution
ENCODE INPUTS (ENC, ENC)
Differential Input Voltage (AC-Coupled)4
Differential Input Resistance
Differential Input Capacitance
A/B MODE INPUTS (A_SEL, B_SEL)5
Input High Voltage Range
Input Low Voltage Range
Full
Full
25°C
25°C
Full
Full
IV
IV
V
V
IV
IV
11
0.4
11
2.5
4.75
0.0
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
POWER CONSUMPTION6
Full II
Full IV
Full II
Full II
Full II
4.75 5.0
3.0 3.3
145
15
775
NOTES
1Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5A_SEL and B_SEL should be tied directly to ground or AVCC.
6Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
Max
240
5.25
0.5
5.25
5.25
182
20
976
DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40؇C, TMAX = +85؇C unless otherwise noted.)
Parameter
Temp
Test
Level
AD6600AST
Min Typ
Max
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)1
Logic Compatibility
Logic “1” Voltage (DVCC = 3.3 V)
Full
Logic “0” Voltage (DVCC = 3.3 V)
Full
Logic “1” Voltage (DVCC = 5.0 V)
Full
Logic “0” Voltage (DVCC = 5.0 V)
Full
Output Coding (D10–D0)
CLK2× OUTPUT1, 2
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Full
Full
Full
Full
II
II
IV
IV
II
II
IV
IV
CMOS
2.8 DVCC – 0.2
0.2 0.5
4.0 DVCC – 0.35
0.35 0.5
Two’s Complement
2.8 DVCC – 0.2
0.2 0.5
4.0 DVCC – 0.3
0.35 0.5
NOTES
1Digital output load is one LCX gate.
2CLK2× output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
–2–
Unit
V p-p
pF
Bits
dB
dB
pF
Bits
V p-p
k
pF
V
V
V
V
mA
mA
mW
Unit
V
V
V
V
V
V
V
V
REV. 0


Part Number AD6600
Description Dual Channel/ Gain-Ranging ADC with RSSI
Maker Analog Devices
Total Page 24 Pages
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