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Analog Devices Semiconductor Electronic Components Datasheet

AD5373 Datasheet

(AD5372 / AD5373) Voltage-Output DACs

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AD5373 pdf
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Preliminary Technical Data
32-Channel, 16/14, Serial Input,
Voltage-Output DACs
AD5372/AD5373
FEATURES
32-channel DAC in 56-LFCSP and 64-LQFP
AD5372 Guaranteed monotonic to 16 bits
AD5373 Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitoring Function
DSP/microcontroller-compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
CONTROL
REGISTER
n
SERIAL
INTERFACE
STATE
MACHINE
n
POWER-ON
RESET
AD5372/
AD5373
n = 16 FOR AD5372
n = 14 FOR AD5373
8 A/B SELECT 8
REGISTER
TO
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n C REGISTER
n A/B
MUX
n
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
14 OFS0 n
REGISTER
OFFSET
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
···
···
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
14 OFS1 n
REGISTER
OFFSET
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
·
···
··
DAC 7
BUFFER
GROUP 1
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VREF1 SUPPLIES
GROUP 2 TO GROUP 3 GROUP 1 TO 3
ARE IDENTICAL TO GROUP 1
5 372-000 1B
Figure 1.
AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending
SIGGND2
SIGGND3
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
VOUT16
TO
VOUT31
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.


Analog Devices Semiconductor Electronic Components Datasheet

AD5373 Datasheet

(AD5372 / AD5373) Voltage-Output DACs

No Preview Available !

AD5373 pdf
AD5372/AD5373
Preliminary Technical Data
TABLE OF CONTENTS
Specifications......................................................................................4
AC Characteristics.........................................................................5
Timing Characteristics .................................................................6
Absolute Maximum Ratings.............................................................8
ESD Caution...................................................................................8
Terminology .................................................................................... 11
Functional Description .................................................................. 12
DAC Architecture—General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Reigsters And Gain/Offset Adjustment.......................... 13
Load DAC.................................................................................... 13
Offset DACs ................................................................................ 13
Output Amplifier........................................................................ 14
Transfer Function ....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
AD5372 Calibration Example................................................... 15
Reset Function ............................................................................ 16
REVISION HISTORY
Pr B1 Modified SPI timing diagrams
Added Reference Selection and Calibration text
Pr. B2 Added Reset Function text
Pr. B3 Added Power Down Mode text
Pr. B4 Added Terminology and Power Supply Sequencing sections
Pr D Rewrote calibration section
Changed SPI read diagram
Pr F. Changed LFCSP Vout8 and Vout9 positions
Clear Function ............................................................................ 16
BUSY and LDAC Functions...................................................... 16
Power-Down Mode .................................................................... 16
Thermal Monitor Function....................................................... 16
Toggle Mode................................................................................ 17
Serial Interface ................................................................................ 18
SPI Write Mode........................................................................... 18
SPI Readback Mode ................................................................... 19
Register Update Rates ................................................................ 19
Channel Addressing And Special Modes ................................ 19
Special Function Mode .............................................................. 20
Power Supply Decoupling ......................................................... 22
Power Supply Sequencing ......................................................... 22
Interfacing Examples...................................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide........................................................................... 24
Rev. PrF| Page 2 of 25


Part Number AD5373
Description (AD5372 / AD5373) Voltage-Output DACs
Maker Analog Devices
Total Page 25 Pages
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