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Analog Devices Semiconductor Electronic Components Datasheet

AD5360 Datasheet

(AD5360 / AD5361) Voltage-Output DAC

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AD5360 pdf
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Preliminary Technical Data
16-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
AD5360/AD5361
FEATURES
16-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V digital interface
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical Line Cards
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
TEMP
SENSOR
CONTROL
REGISTER
8
VOUT0 -
VOUT15
MUX
6
GPIO
REGISTER
2
SERIAL
INTERFACE
AD5360, n = 16
AD5361, n = 14
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n X1A REGISTER MUX n
n
n X1B REGISTER
n
1n
M REGISTER
n C REGISTER
n
STATE
MACHINE
n
POWER-ON
RESET
AD5360/
AD5361
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
X1A REGISTER
n
MUX
n
n X1B REGISTER
n
1
n
M REGISTER
n C REGISTER
n
14 OFS0 14 OFFSET
REGISTER
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
··
····
DAC 7
14 OFS1 14 OFFSET
REGISTER
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
··
····
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
···
·
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·····
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5360-0001
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
Figure 1.
AD5360/AD5361—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.


Analog Devices Semiconductor Electronic Components Datasheet

AD5360 Datasheet

(AD5360 / AD5361) Voltage-Output DAC

No Preview Available !

AD5360 pdf
AD5360/AD5361
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Functional Description .................................................................. 12
DAC Architecture—General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Registers Gain/Offset Adjustment .................................. 13
Offset DACS................................................................................ 13
Output Amplifier........................................................................ 14
Transfer Function ....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
AD5360 Calibration Example................................................... 15
Reset Function ............................................................................ 15
Preliminary Technical Data
Clear Function ............................................................................ 16
BUSY and LDAC Functions...................................................... 16
Monitor Function....................................................................... 17
GPIO Pin ..................................................................................... 17
Power-Down Mode.................................................................... 17
Thermal Monitoring Function ................................................. 17
Toggle Mode................................................................................ 17
Serial Interface ................................................................................ 18
SPI Write Mode .......................................................................... 18
Register Update Rates ................................................................ 18
SPI Readback Mode ................................................................... 19
Channel Addressing And Special Modes................................ 19
Special Function Mode.............................................................. 20
Power Supply Decoupling ......................................................... 22
Power Supply Sequencing ......................................................... 22
Interfacing Examples ................................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
Pr B2.
Pr F
Modified SPI Timing Diagrams
Added Reference Selection and Calibration text
rewrote calibration section
Changed SPI read diagram
Rev. PrF | Page 2 of 25


Part Number AD5360
Description (AD5360 / AD5361) Voltage-Output DAC
Maker Analog Devices
Total Page 25 Pages
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