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Analog Devices Semiconductor Electronic Components Datasheet

AD5344 Datasheet

Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs

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AD5344 pdf
a 2.5 V to 5.5 V, 500 A, Parallel Interface
Quad Voltage-Output 8-/10-/12-Bit DACs
AD5334/AD5335/AD5336/AD5344*
FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both sup-
ply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5334 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA/B
VDD
GAIN
DB... 7
DB0
CS
WR
A0
A1
POWER-ON
RESET
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INTER-
FACE
LOGIC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INPUT
DAC
REGISTER REGISTER
8-B8I-TBIT
DADCAC
AD5334
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
CLR
LDAC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
BUFFER
VOUTD
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREFC/D
PD GND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


Analog Devices Semiconductor Electronic Components Datasheet

AD5344 Datasheet

Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs

No Preview Available !

AD5344 pdf
AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 kto GND; CL =200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1
B Version2
Min Typ Max
Unit
Conditions/Comments
DC PERFORMANCE3, 4
AD5334
Resolution
Relative Accuracy
Differential Nonlinearity
AD5335/AD5336
Resolution
Relative Accuracy
Differential Nonlinearity
AD5344
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband5
Upper Deadband
Offset Error Drift6
Gain Error Drift6
DC Power Supply Rejection Ratio6
DC Crosstalk6
8
± 0.15
± 0.02
10
± 0.5
± 0.05
12
±2
± 0.2
± 0.4
± 0.1
10
10
–12
–5
–60
200
±1
± 0.25
±4
± 0.5
± 16
±1
±3
±1
60
60
Bits
LSB
LSB Guaranteed Monotonic By Design Over All Codes
Bits
LSB
LSB Guaranteed Monotonic By Design Over All Codes
Bits
LSB
LSB
% of FSR
% of FSR
mV
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
Guaranteed Monotonic By Design Over All Codes
Lower Deadband Exists Only if Offset Error Is Negative
VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
VDD = ± 10%
RL = 2 kto GND, 2 kto VDD; CL = 200 pF to GND;
Gain = 0
DAC REFERENCE INPUT6
VREF Input Range
VREF Input Impedance
Reference Feedthrough
Channel-to-Channel Isolation
0.25
180
90
90
45
–90
–90
VDD
V
k
k
k
k
dB
dB
Gain = 1. Input Impedance = RDAC (AD5336/AD5344)
Gain = 2. Input Impedance = RDAC (AD5336)
Gain = 1. Input Impedance = RDAC (AD5334/AD5335)
Gain = 2. Input Impedance = RDAC (AD5334)
Frequency = 10 kHz
Frequency = 10 kHz
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS6
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
0.001
VDD – 0.001
0.5
50
20
2.5
5
±1
0.8
0.6
0.5
2.4
2.1
2.0
3.5
V min
V max
mA
mA
µs
µs
µA
V
V
V
V
V
V
pF
Rail-to-Rail Operation
VDD = 5 V
VDD = 3 V
Coming Out of Power-Down Mode. VDD = 5 V
Coming Out of Power-Down Mode. VDD = 3 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
2.5 5.5
600 900
500 700
0.2 1
0.08 1
V
µA
µA
µA
µA
All DACs active and excluding load currents.
VIH = VDD, VIL = GND.
IDD increases by 50 µA at VREF > VDD – 100 mV.
NOTES
1See Terminology section.
2Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
3Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095).
4DC specifications tested with outputs unloaded.
5This corresponds to x codes. x = Deadband voltage/LSB size.
6Guaranteed by design and characterization, not production tested.
7In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V REF = VDD and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2– REV. 0


Part Number AD5344
Description Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs
Maker Analog Devices
Total Page 20 Pages
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