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Analog Devices Semiconductor Electronic Components Datasheet

AD5321 Datasheet

+2.5 V to +5.5 V/ 120 uA/ 2-Wire Interface/ Voltage Output 8-/10-/12-Bit DACs

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AD5321 pdf
a +2.5 V to +5.5 V, 120 A, 2-Wire Interface,
Voltage Output 8-/10-/12-Bit DACs
AD5301/AD5311/AD5321*
FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead SOIC Packages
Micropower Operation: 120 A @ 3 V
2-Wire (I2C® Compatible) Serial Interface
Data Readback Capability
+2.5 V to +5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
On-Chip Rail-to-Rail Output Buffer Amplifier
Three Power-Down Functions
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit
buffered voltage-output DACs that operate from a single +2.5 V
to +5.5 V supply consuming 120 µA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/µs. It uses a 2-wire (I2C compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on-reset circuit, which ensures that
the DAC output powers-up to zero volts and remains there until
a valid write takes place. The parts contain a power-down feature
which reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V
reducing to 1 µW in all power-down modes.
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5301/AD5311/AD5321
SCL
REF
SDA
A0
A1*
INTERFACE
LOGIC
DAC
REGISTER
8-/10-/12-BIT
DAC
BUFFER
POWER-DOWN
LOGIC
VOUT
POWER-ON
RESET
RESISTOR
NETWORK
GND
*AVAILABLE ON 8-LEAD VERSION ONLY
PD*
I2C is a registered trademark of Philips Corporation.
*Protected by U.S. Patent No. 5684481, other patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999


Analog Devices Semiconductor Electronic Components Datasheet

AD5321 Datasheet

+2.5 V to +5.5 V/ 120 uA/ 2-Wire Interface/ Voltage Output 8-/10-/12-Bit DACs

No Preview Available !

AD5321 pdf
AD5301/AD5311/AD5321–SPECIFICATIONS (VDD = +2.5 V to +5.5 V; RL = 2 kto GND;
CL = 200 pF to GND; All specifications TMIN to TMAX unless otherwise noted.)
Parameter1
B Version2
Min Typ Max
Units
Conditions/Comments
DC PERFORMANCE3, 4
AD5301
Resolution
Relative Accuracy
Differential Nonlinearity
AD5311
Resolution
Relative Accuracy
Differential Nonlinearity
AD5321
Resolution
Relative Accuracy
Differential Nonlinearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift5
Gain Error Drift5
8
± 0.15
± 0.02
10
± 0.5
± 0.05
12
±2
± 0.3
+5
± 0.15
± 0.15
–20
–5
±1
± 0.25
±4
± 0.5
± 16
± 0.8
+20
± 1.25
±1
Bits
LSB
LSB Guaranteed Monotonic by Design Over All Codes
Bits
LSB
LSB Guaranteed Monotonic by Design Over All Codes
Bits
LSB
LSB
mV
% of FSR
% of FSR
µV/°C
ppm of FSR/°C
Guaranteed Monotonic by Design Over All Codes
All Zeros Loaded to DAC, See Figure 9
All Ones Loaded to DAC, See Figure 9
OUTPUT CHARACTERISTICS5
Minimum Output Voltage
Maximum Output Voltage
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS (A0, A1, PD)5
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
0.001
VDD – 0.001
1
50
20
2.5
6
2.4
2.1
2.0
3
±1
0.8
0.6
0.5
V min
V max
mA
mA
µs
µs
µA
V
V
V
V
V
V
pF
This is a measure of the minimum and maximum drive
capability of the output amplifier.
VDD = +5 V
VDD = +3 V
Coming Out of Power-Down Mode. VDD = +5␣ V
Coming Out of Power-Down Mode. VDD = +3␣ V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
LOGIC INPUTS (SCL, SDA)5
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection6
0.7 VDD
–0.3
0.05 VDD
6
VDD + 0.3
0.3 VDD
±1
50
V
V
µA
V
pF
ns
VIN = 0 V to VDD
Pulsewidth of Spike Suppressed
LOGIC OUTPUT (SDA)5
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
0.4 V
0.6 V
± 1 µA
6 pF
ISINK = 3 mA
ISINK = 6 mA
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
IDD (Power-Down Mode)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
2.5 5.5
150 250
120 220
0.2 1
0.05 1
V
µA
µA
µA
µA
IDD Specification Is Valid for All DAC Codes
DAC Active and Excluding Load Current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
NOTES
1See Terminology.
2Temperature ranges are as follows: B Version: –40°C to +105°C.
3DC specifications tested with the outputs unloaded.
4Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000).
5Guaranteed by Design and Characterization, not production tested.
6Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice .
–2– REV. 0


Part Number AD5321
Description +2.5 V to +5.5 V/ 120 uA/ 2-Wire Interface/ Voltage Output 8-/10-/12-Bit DACs
Maker Analog Devices
Total Page 15 Pages
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