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Analog Devices Semiconductor Electronic Components Datasheet

AD5303 Datasheet

+2.5 V to +5.5 V/ 230 uA/ Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

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AD5303 pdf
a +2.5 V to +5.5 V, 230 A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323*
FEATURES
AD5303: Two Buffered 8-Bit DACs in One Package
AD5313: Two Buffered 10-Bit DACs in One Package
AD5323: Two Buffered 12-Bit DACs in One Package
16-Lead TSSOP Package
Micropower Operation: 300 A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On-Reset to Zero Volts
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single +2.5 V to +5.5 V supply consuming 230 µA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/
AD5313/AD5323 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on-reset circuit that ensures that the DAC outputs power-up to
0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and
provides software-selectable output loads while in power-down
mode. The parts may also be used in daisy-chaining applications
using the SDO pin.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD
BUF A
VREFA
SYNC
SCLK
DIN
POWER-ON
RESET
INPUT
REGISTER
INTERFACE
LOGIC
>
DAC
REGISTER
AD5303/AD5313/AD5323
STRING
DAC
BUFFER
POWER-DOWN
LOGIC
VOUTA
RESISTOR
NETWORK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
BUFFER
VOUTB
SDO
GAIN-SELECT
LOGIC
RESISTOR
NETWORK
DCEN LDAC CLR
PD
*Protected by U.S. Patent No. 5684481; other patents pending.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
BUF B
VREFB
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999


Analog Devices Semiconductor Electronic Components Datasheet

AD5303 Datasheet

+2.5 V to +5.5 V/ 230 uA/ Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

No Preview Available !

AD5303 pdf
AD5303/AD5313/AD5323–SPECIFICATIONS
(VDD = +2.5 V to +5.5 V; VREF = +2 V; RL = 2 kto GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1
B Version2
Min Typ
Max
Units
Conditions/Comments
DC PERFORMANCE3, 4
AD5303
Resolution
Relative Accuracy
Differential Nonlinearity
AD5313
Resolution
Relative Accuracy
Differential Nonlinearity
AD5323
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift5
Gain Error Drift5
Power Supply Rejection Ratio5
DC Crosstalk5
DAC REFERENCE INPUTS5
VREF Input Range
VREF Input Impedance
1
0
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6
Maximum Output Voltage6
DC Output Impedance
Short Circuit Current
Power-Up Time
LOGIC INPUTS5
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
LOGIC OUTPUT (SDO)5
VDD = +5 V ± 10%
Output Low Voltage
Output High Voltage
VDD = +3 V ± 10%
Output Low Voltage
Output High Voltage
Floating-State Leakage Current
Floating State O/P Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
IDD (Full Power-Down)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
2.4
2.1
2.0
4.0
2.4
2.5
8
± 0.15
± 0.02
10
± 0.5
± 0.05
12
±2
± 0.2
± 0.4
± 0.15
10
–12
–5
–60
30
±1
± 0.25
±3
± 0.5
± 12
±1
±3
±1
60
>10
VDD
VDD
180
90
–90
–80
0.001
VDD – 0.001
0.5
50
20
2.5
5
±1
0.8
0.6
0.5
2 3.5
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
% of FSR
% of FSR
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
V
V
M
k
k
dB
dB
V min
V max
mA
mA
µs
µs
µA
V
V
V
V
V
V
pF
Guaranteed Monotonic by Design Over All Codes
Guaranteed Monotonic by Design Over All Codes
Guaranteed Monotonic by Design Over All Codes
See Figures 3 and 4
See Figures 3 and 4
See Figures 3 and 4
VDD = ± 10%
Buffered Reference Mode
Unbuffered Reference Mode
Buffered Reference Mode
Unbuffered Reference Mode. 0–VREF Output Range,
Input Impedance = RDAC
Unbuffered Reference Mode. 0–2 VREF Output Range,
Input Impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz
This is a measure of the minimum and maximum
drive capability of the output amplifier.
VDD = +5 V
VDD = +3 V
Coming Out of Power-Down Mode. VDD = +5 V
Coming Out of Power-Down Mode. VDD = +3 V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
VDD = +5 V ± 10%
VDD = +3 V ± 10%
VDD = +2.5 V
0.4 V
V
0.4 V
V
1 µA
3 pF
5.5 V
300 450 µA
230 350 µA
0.2 1 µA
0.05 1 µA
ISINK = 2 mA
ISOURCE = 2 mA
ISINK = 2 mA
ISOURCE = 2 mA
DCEN = GND
DCEN = GND
IDD Specification Is Valid for All DAC Codes
Both DACs Active and Excluding Load Currents
Both DACs in Unbuffered Mode. VIH = VDD and
VIL = GND. In Buffered Mode, extra current is
typically x µA per DAC where x = 5 µA + VREF/RDAC.
–2– REV. 0


Part Number AD5303
Description +2.5 V to +5.5 V/ 230 uA/ Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs
Maker Analog Devices
Total Page 18 Pages
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