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Analog Devices Semiconductor Electronic Components Datasheet

AD5204 Datasheet

4-/6-Channel Digital Potentiometers

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AD5204 pdf
a
FEATURES
256 Position
Multiple Independently Programmable Channels
AD5204—4-Channel
AD5206—6-Channel
Potentiometer Replacement
10 k, 50 k, 100 k
3-Wire SPI-Compatible Serial Data Input
+2.7 V to +5.5 V Single Supply; ؎2.7 V Dual Supply
Operation
Power ON Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
4-/6-Channel
Digital Potentiometers
AD5204/AD5206
FUNCTIONAL BLOCK DIAGRAMS
CS
CLK
SDO
A2
A1
DO A0
D7
EN
ADDR
DEC
SER
REG
SDI
GND
DI D0
POWER-
ON
PRESET
8
AD5204
D7
RDAC
LATCH
#1
D0 R
D7
RDAC
LATCH
#4
D0
R
VDD
A1
W1
B1
A4
W4
B4
SHDN
VSS
PR
GENERAL DESCRIPTION
The AD5204/AD5206 provides four-/six-channel, 256 position
digitally-controlled Variable Resistor (VR) devices. These de-
vices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5204/
AD5206 contains a fixed resistor with a wiper contact that taps
the fixed resistor value at a point determined by a digital code
loaded into the SPI-compatible serial-input register. The resis-
tance between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. The variable resistor offers a completely program-
mable value of resistance between the A terminal and the wiper
or the B Terminal and the wiper. The fixed A-to-B terminal
resistance of 10 k, 50 k, or 100 khas a nominal tempera-
ture coefficient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eleven data bits make up
the data word clocked into the serial input register. The first
three bits are decoded to determine which VR latch will be
loaded with the last eight bits of the data word when the CS
strobe is returned to logic high. A serial data output pin at
the opposite end of the serial register (AD5204 only) allows
simple daisy-chaining in multiple VR applications without
additional external decoding logic.
CS
CLK
EN
A2
A1
ADDR
DEC
A0
D7
SER
REG
SDI
GND
DI D0
POWER-
ON
PRESET
8
AD5206
D7
RDAC
LATCH
#1
D0 R
D7
RDAC
LATCH
#6
D0 R
VDD
A1
W1
B1
A6
W6
B6
VSS
An optional reset (PR) pin forces all the AD5204 wipers to the
midscale position by loading 80H into the VR latch.
The AD5204/AD5206 is available in both surface mount
(SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For additional single,
dual, and quad channel devices, see the AD8400/AD8402/
AD8403 products.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999


Analog Devices Semiconductor Electronic Components Datasheet

AD5204 Datasheet

4-/6-Channel Digital Potentiometers

No Preview Available !

AD5204 pdf
AD5204/AD5206–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VDD = +5 V ؎ 10% or +3 V ؎ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40؇C < TA < +85؇C
unless otherwise noted.)
Parameter
Symbol
Conditions
Min Typ1 Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL2
Resistor Nonlinearity Error2
Nominal Resistor Tolerance3
R-DNL
R-INL
RAB
RWB, VA = No Connect
RWB, VA = No Connect
TA = +25°C
Resistance Temperature Coefficient
RAB/T
VAB = VDD, Wiper = No Connect
Nominal Resistance Match
R/RAB
CH1 to 2, 3, 4, or 5, 6; VAB = VDD
Wiper Resistance
RW IW = 1 V/R, VDD = +5 V
–1 ± 1/4 +1
–2 ± 1/2 +2
–30 +30
700
0.25 1.5
50 100
LSB
LSB
%
ppm/°C
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
Differential Nonlinearity4
DNL
Integral Nonlinearity4
INL
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
VW/T
VWFSE
VWZSE
Code = 40H
Code = 7FH
Code = 00H
8
–1 ± 1/4 +1
–2 ± 1/2 +2
15
–2 –1
0
0 +1 +2
Bits
LSB
LSB
ppm/°C
LSB
LSB
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Current7
Common-Mode Leakage
VA, VB, VW
CA, CB
CW
IA_SD
ICM
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
VSS
VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V
45
60
0.01
1
VDD
5
V
pF
pF
µA
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VOH
VOL
IIL
CIL
VDD = +5 V/+3 V
VDD = +5 V/+3 V
RPULL–UP = 1 kto +5 V
IOL = 1.6 mA, VLOGIC = +5 V
VIN = 0 V or +5 V
2.4/2.1
4.9
5
0.8/0.6
0.4
±1
V
V
V
V
µA
pF
POWER SUPPLIES
Power Single Supply Range
Power Dual Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation8
Power Supply Sensitivity
VDD Range
VDD/SS Range
IDD
ISS
PDISS
PSS
VSS = 0 V
VIH = +5 V or VIL = 0 V
VSS = –2.5 V, VDD = +2.7 V
VIH = +5 V or VIL = 0 V
VDD = +5 V ± 10%
2.7
± 2.3
12
12
0.0002
5.5
± 2.7
60
60
0.3
0.005
V
V
µA
µA
mW
%/%
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time (10K/50K/100K)
Resistor Noise Voltage
BW_10K
BW_50K
BW_100K
THDW
tS
eN_WB
RAB = 10 k
RAB = 50 k
RAB = 100 k
VA = 1.414 V rms, VB = 0 V dc, f = 1 kHz
VA = 5 V, VB = 0 V, ± 1 LSB Error Band
RWB = 5 k, f = 1 kHz, PR = 0
721
137
69
0.004
2/9/18
9
kHz
kHz
kHz
%
µs
nV/Hz
INTERFACE TIMING CHARACTERISTICS Applies to All Parts6, 10
Input Clock Pulsewidth
tCH, tCL
Clock Level High or Low
Data Setup Time
tDS
Data Hold Time
CLK to SDO Propagation Delay11
CS Setup Time
CS High Pulsewidth
tDH
tPD
tCSS
tCSW
RL = 2 k, CL < 20 pF
Reset Pulsewidth
CLK Fall to CS Fall Setup
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tRS
tCSH0
tCSH1
tCS1
20 ns
5 ns
5 ns
1 150 ns
15 ns
40 ns
90 ns
0 ns
0 ns
10 ns
NOTES
1Typicals represent average readings at +25°C and VDD = +5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
–2– REV. 0


Part Number AD5204
Description 4-/6-Channel Digital Potentiometers
Maker Analog Devices
Total Page 11 Pages
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