http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf



Analog Devices Semiconductor Electronic Components Datasheet

AD1895 Datasheet

192 kHz Stereo Asynchronous Sample Rate Converter

No Preview Available !

AD1895 pdf
a
192 kHz Stereo Asynchronous
Sample Rate Converter
AD1895*
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V–5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1895 TDM Daisy-Chain Mode
128 dB Signal-to-Noise and Dynamic Range
(A-Weighted, 20 Hz–20 kHz BW)
Up to –122 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256 ؋ fS, 512 ؋ fS or 768 ؋ fS Master Mode
Clock
Flexible Three-Wire Serial Data Port with Left-Justified,
I2S, Right-Justified (16-, 18-, 20-, 24-Bits), and TDM
Serial Port Modes
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Automotive Audio Systems,
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio
Effects Processors
PRODUCT OVERVIEW
The AD1895 is a 24-bit, high-performance, single-chip, second-
generation asynchronous sample rate converter. Based upon
Analog Devices, Inc. experience with its first asynchronous
sample rate converter, the AD1890, the AD1895 offers improved
performance and additional features. This improved performance
includes a THD + N range of –115 dB to –122 dB depending
on sample rate and input frequency, 128 dB (A-Weighted)
dynamic range, 192 kHz sampling frequencies for both input and
output sample rates, improved jitter rejection, and 1:8 upsampling
and 7.75:1 downsampling ratios. Additional features include
more serial formats, a bypass mode, and better interfacing to
digital signal processors.
The AD1895 has a 3-wire interface for the serial input and
output ports that supports left-justified, I2S, and right-justified
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM mode for daisy chaining multiple AD1895s to
FUNCTIONAL BLOCK DIAGRAM
RESET VDD_IO VDD_CORE
MUTE_I
SDATA_I
SCLK_I
LRCLK_I
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
BYPASS
MUTE_O
SERIAL
INPUT
FIFO
DIGITAL
PLL
AD1895
FSOUT
FSIN
FIR
FILTER
SERIAL
OUTPUT
SDATA_O
SCLK_O
LRCLK_O
TDM_IN
SMODE_O_0
SMODE_O_1
CLOCK DIVIDER
ROM
WLNGTH_O_0
WLNGTH_O_1
MCLK_I MSMODE_0 MSMODE_2
MCLK_O MSMODE_1
a digital signal processor. The serial output data is dithered down
to 20, 18 or 16 bits when 20-, 18- or 16-bit output data is selected.
The AD1895 sample rate converts the data from the serial input
port to the sample rate of the serial output port. The sample rate
at the serial input port can be asynchronous with respect to the
output sample rate of the output serial port. The master clock to
the AD1895, MCLK, can be asynchronous to both the serial
input and output ports.
MCLK can either be generated off-chip or on-chip by the AD1895
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1895 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1895 supports master modes of 256 × fS, 512 × fS, and
768 × fS for both input and output serial ports.
Conceptually, the AD1895 interpolates the serial input data by
a rate of 220 and samples the interpolated data stream by the
output sample rate. In practice, a 64-tap FIR filter with 220
polyphases, a FIFO, a digital servo loop that measures the time
difference between input and output samples within 5 ps, and a
digital circuit to track the sample rate ratio are used to perform
the interpolation and output sampling. Refer to the Theory of
Operation section. The digital servo loop and sample rate ratio
circuit automatically track the input and output sample rates.
*Patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
(Continued on page 15)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001



Analog Devices Semiconductor Electronic Components Datasheet

AD1895 Datasheet

192 kHz Stereo Asynchronous Sample Rate Converter

No Preview Available !

AD1895 pdf
AD1895–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
VDD_CORE
3.3 V
VDD_IO
5.0 V or 3.3 V
Ambient Temperature
25°C
Input Clock
30.0 MHz
Input Signal
1.000 kHz, 0 dBFS
Measurement Bandwidth 20 to fS_OUT/2 Hz
Word Width
24 Bits
Load Capacitance
50 pF
Input Voltage HI
2.4 V
Input Voltage LO
0.8 V
Specifications subject to change without notice.
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V ؎ 5%, VDD_IO = 5.0 V ؎ 10%)
Parameter
Min Typ Max
Resolution
Sample Rate @ MCLK_I = 30 MHz
Sample Rate (@ Other Master Clocks)1
Sample Rate Ratios
Upsampling
Downsampling
Dynamic Range2
(20 Hz to fS_OUT/2, 1 kHz, –60 dBFS Input) A-Weighted
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
96 kHz: 48 kHz
192 kHz: 32 kHz
(20 Hz to fS_OUT/2, 1 kHz, –60 dBFS Input) No Filter
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
96 kHz: 48 kHz
192 kHz: 32 kHz
Total Harmonic Distortion + Noise2
(20 Hz to fS_OUT/2, 1 kHz, 0 dBFS Input) No Filter
Worst-Case (48 kHz:96 kHz)3
44.1 kHz: 48 kHz
48 kHz: 44.1 kHz
48 kHz: 96 kHz
44.1 kHz: 192 kHz
96 kHz: 48 kHz
192 kHz: 32 kHz
Interchannel Gain Mismatch
Interchannel Phase Deviation
Mute Attenuation (24 Bits Word Width)
24
6 215
MCLK_I/5000 fS_OUT MCLK_I/138
1:8
7.75:1
128
128
128
128
127
127
125
125
125
125
124
124
–115
–120
–119
–118
–120
–122
–122
0.0
0.0
–127
NOTES
1Lower sampling rates than given by this formula are possible, but the jitter rejection will decrease.
2Refer to the Typical Performance Characteristics section for DNR and THD+N numbers over wide range of Input and Output Sample Rates.
3For any other ratio, minimum THD+N will be better than –115 dB. Please refer to detailed performance plots.
Specifications subject to change without notice.
Unit
Bits
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degrees
dB
–2– REV. A



Analog Devices Semiconductor Electronic Components Datasheet

AD1895 Datasheet

192 kHz Stereo Asynchronous Sample Rate Converter

No Preview Available !

AD1895 pdf
DIGITAL TIMING (–40؇C < TA < +105؇C, VDD_CORE = 3.3 V ؎ 5%, VDD_IO = 5.0 V ؎ 10%)
Parameter1
Min
tMCLKI
fMCLK
tMPWH
tMPWL
MCLK_I Period
MCLK_I Frequency
MCLK_I Pulsewidth High
MCLK_I Pulsewidth Low
33.3
8
12
Input Serial Port Timing
tLRIS LRCLK_I Setup to SCLK_I
tSIH SCLK_I Pulsewidth High
tSIL SCLK_I Pulsewidth Low
tDIS SDATA_I Setup to SCLK_I Rising Edge
tDIH SDATA_I Hold from SCLK_I Rising Edge
8
8
8
8
3
Output Serial Port Timing
tTDMS
tTDMH
tDOPD
tDOH
tLROS
tLROH
tSOH
tSOL
tRSTL
TDM_IN Setup to SCLK_O Falling Edge
TDM_IN Hold from SCLK_O Falling Edge
SDATA_O Propagation Delay from SCLK_O, LRCLK_O
SDATA_O Hold from SCLK_O
LRCLK_O Setup to SCLK_O (TDM Mode Only)
LRCLK_O Hold from SCLK_O (TDM Mode Only)
SCLK_O Pulsewidth High
SCLK_O Pulsewidth Low
RESET Pulsewidth LO
3
3
3
5
3
10
5
NOTES
1Refer to Timing Diagram Section.
2The maximum possible sample rate is: FSMAX = fMCLK /138.
3fMCLK of up to 34 MHz is possible under the following conditions: 0°C < TA < 70°C, 45/55 or better MCLK_I duty cycle.
Specifications subject to change without notice.
Max
30.02, 3
20
200
TIMING DIAGRAMS
LRCLK_I
SCLK I
SDATA I
tLRIS
tDIS
tDIH
tSIH
tSIL
LRCLK O
SCLK O
tDOPD
SDATA O
LRCLK O
tLROS
tLROH
tSOH
tSOL
tDOH
SCLK O
TDM IN
tTDMS
tTDMH
Figure 1. Input and Output Serial Port Timing (SCLK I/O,
LRCLK I/O, SDATA I/O, TDM_IN)
MCLK I
RESET
tRSTL
Figure 2. RESET Timing
tMPWH
tMPWL
Figure 3. MCLK_I Timing
AD1895
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. A
–3–




Part Number AD1895
Description 192 kHz Stereo Asynchronous Sample Rate Converter
Maker Analog Devices
Total Page 24 Pages
PDF Download
AD1895 pdf
Download PDF File
AD1895 pdf
View for Mobile






Related Datasheet

1 AD1890 SamplePort Stereo Asynchronous Sample Rate Converters Analog Devices
Analog Devices
AD1890 pdf
2 AD1891 SamplePort Stereo Asynchronous Sample Rate Converters Analog Devices
Analog Devices
AD1891 pdf
3 AD1892 Integrated Digital Receiver/Rate Converter Analog Devices
Analog Devices
AD1892 pdf
4 AD1893 Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter Analog Devices
Analog Devices
AD1893 pdf
5 AD1895 192 kHz Stereo Asynchronous Sample Rate Converter Analog Devices
Analog Devices
AD1895 pdf
6 AD1896 192 kHz Stereo Asynchronous Sample Rate Converter Analog Devices
Analog Devices
AD1896 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components