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Analog Devices Semiconductor Electronic Components Datasheet

AD1876 Datasheet

16-Bit 100 kSPS Sampling ADC

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AD1876 pdf
a
FEATURES
Autocalibrating
0.002% THD
90 dB S/(N+D)
1 MHz Full Power Bandwidth
On-Chip Sample & Hold Function
2؋ Oversampling for Audio Applications
16-Pin DIP Package
Serial Twos Complement Output Format
Low Input Capacitance–typ 50 pF
AGND Sense for Improved Noise Immunity
16-Bit 100 kSPS
Sampling ADC
AD1876
FUNCTIONAL BLOCK DIAGRAM
VIN 10
AGND SENSE 9
VREF 11
AGND 8
INPUT
BUFFERS
16-BIT
DAC
CAL
DAC
A CHIP
COMP
LOGIC TIMING
LEVEL TRANSLATORS
PRODUCT DESCRIPTION
The AD1876 is a 16-bit serial output sampling A/D converter
which uses a switched capacitor/charge redistribution architecture
to achieve a 100 kSPS conversion rate (10 µs total conversion
time). Overall performance is optimized by digitally correcting
internal nonlinearities through on-chip autocalibration.
The circuitry of the AD1876 is partitioned onto two monolithic
chips, a digital control chip fabricated with Analog Devices’
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
package.
The serial output interface requires an external clock and
sample command signal. The output data rate may be as high
as 2.08 MHz, and is controlled by the external clock. The twos
complement format of the output data is MSB first and is di-
rectly compatible with the NPC SM5805 digital decimation fil-
ter used in consumer audio products. The AD1876 is also
compatible with a variety of DSP processors.
The AD1876 is packaged in a space saving 16-pin plastic DIP
and operates from +5 V and ± 12 V supplies; typical power con-
sumption is 235 mW. The digital supply (VDD) is isolated from
the linear supplies (VEE and VCC) for reduced digital crosstalk.
Separate analog and digital grounds are also provided.
CAL 16
CLK 2
SAMPLE 1
MICROCODED
CONTROLLER
SAR
ALU
15 BUSY
14 D OUT CLK
3 DOUT
RAM
D CHIP
AD1876
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703



Analog Devices Semiconductor Electronic Components Datasheet

AD1876 Datasheet

16-Bit 100 kSPS Sampling ADC

No Preview Available !

AD1876 pdf
AD1876–SPECIFICATIONS (TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%)1
Parameter
AD1876J
Min Typ
Max
Units
TEMPERATURE RANGE
TOTAL HARMONIC DISTORTION (THD)2
–0.05 dB Input
–20 dB Input
–60 dB Input
0 70 °C
–95
0.002
–78
0.01
–40
1.0
–88
0.004
dB
%
dB
%
dB
%
D-RANGE, –60 dB, A-WEIGHTED
SIGNAL-TO-NOISE AND DISTORTION (S/(N+D)) RATIO3
–0.05 dB Input, A-Weighted
–0.05 dB Input, 48 kHz Bandwidth
–20 dB Input, A-Weighted
–20 dB Input, 48 kHz Bandwidth
–60 dB Input, A-Weighted
–60 dB Input, 48 kHz Bandwidth
83
92
92
90
73
70
34
31
dB
dB
dB
dB
dB
dB
dB
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
INTERMODULATION DISTORTION (IMD)4
2nd Order Products
3rd Order Products
–99
–102
–98
–89
dB
dB
dB
FULL POWER BANDWIDTH
1 MHz
VOLTAGE REFERENCE INPUT RANGE5 (VREF)
ANALOG INPUT6
Input Range (VIN)
Input Impedance
Input Capacitance During Sample
Aperture Delay
Aperture Jitter
35
10.0 V
± VREF
V
*
50* pF
6 ns
100 ps
POWER SUPPLIES
Operating Current
ICC
IEE
IDD
Power Consumption
9 12
9 12
3 12
235 350
mA
mA
mA
mW
NOTES
1VREF = 5.00 V; conversion rate = 96 kSPS; fIN = 1.06 kHz; VIN = –0.05 dB unless otherwise noted. All measurements referred to a 0 dB (10 V p-p) input signal.
Values are post calibration.
2Includes first 19 harmonics.
3Minimum value of S/(N+D) corresponds to 5.0 V reference; typical values of S/(N+D) correspond to 10.0 V reference.
4fa = 1008 Hz; fb = 1055 Hz. See Definition of Specifications section and Figure 14.
5See Applications section for recommended voltage reference circuit and Figure 11 for performance with other reference voltage values.
6See Applications section for recommended input buffer circuit.
*For explanation of input characteristics, see “Analog Input” section.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
ORDERING GUIDE
Model
Temperature THD Package
Range
dB Description
Package
Option*
AD1876JN 0°C to +70°C –95 Plastic 16-Pin DIP N-16
*N = Narrow Plastic DIP.
–2– REV. A



Analog Devices Semiconductor Electronic Components Datasheet

AD1876 Datasheet

16-Bit 100 kSPS Sampling ADC

No Preview Available !

AD1876 pdf
AD1876
DIGITAL SPECIFICATIONS (TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%)
Parameter
Test Conditions
Min
Typ
Max
Units
LOGIC INPUTS
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIH High Level Input Current
IIL Low Level Input Current
CIN Input Capacitance
LOGIC OUTPUTS
VOH High Level Output Voltage
VOL Low Level Output Voltage
VIH = VDD
VIL = 0 V
IOH = 0.1 mA
IOH = 0.5 mA
IOL = 1.6 mA
2.4
–0.3
–10
–10
VDD – 1 V
2.4
V
0.8 V
+10 µA
+10 µA
10 pF
V
V
0.4 V
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at worst case temperature. Results from those tests are used to calculate outgoing qual-
ity levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
ABSOLUTE MAXIMUM RATINGS*
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V
Analog Inputs, VREF to AGND . . . . . . . . . . . (VCC + 0.3 V) to
(VEE – 0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING SPECIFICATIONS1
(TMIN to TMAX, VCC = +12 V ؎ 5%, VEE = –12 V ؎ 5%, VDD = +5 V ؎ 10%, VREF = 5.00 V)
Parameter
Symbol
Min
Typ
Max
Units
Sampling Rate2
fS = 1/tS
1
100 kSPS
Sampling Period2
tS = l/fS
10
1000
µs
Acquisition Time (Included in tS)
tA
2
µs
Calibration Time
tCT
5000
tC
CLK Period
tC 480
ns
CAL to BUSY Delay
tCALB
0
ns
CLK to BUSY Delay
tCB 50 120 175 ns
CLK to DOUT Hold Time
tCD 10
ns
CLK HIGH
tCH 160
ns
CLK LOW
tCL 50
ns
DOUT CLK LOW
tDCL 30 80 200 ns
SAMPLE LOW to 1st CLK Delay
tSC
50
ns
CAL HIGH Time
tCALH
4
tC
CLK to DOUT CLK
tCDH
150 200 275 ns
SAMPLE LOW
tSL 50
ns
NOTES
1See Figure 1 and Figure 2 and the Conversion Control and Autocalibration sections for detailed explanations of the above timing.
2Depends upon external clock frequency; includes acquisition time and conversion time. The minimum sampling rate/maximum sampling period is specified to
account for droop of the internal sample/hold. Operation at slower rates than specified may degrade performance.
REV. A
–3–




Part Number AD1876
Description 16-Bit 100 kSPS Sampling ADC
Maker Analog Devices
Total Page 12 Pages
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