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Analog Devices Semiconductor Electronic Components Datasheet

AD1859 Datasheet

Stereo/ Single-Supply 18-Bit Integrated DAC

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AD1859 pdf
a
Stereo, Single-Supply
18-Bit Integrated ⌺⌬ DAC
AD1859
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit ⌺⌬ Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 kOutput Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components
؎0.1؇ Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I2S-Justified, Left-Justified,
Right-Justified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
PRODUCT OVERVIEW
The AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (∑∆)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
The key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous ∑∆ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
single bit ∑∆ DACs is also dependent on the spectral purity of
the sample and master clocks. The AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
The AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
SUPPLY
2
CONTROL
DATA
INPUT
3
REFERENCE
FILTER AND
GROUND
2
ASYNCHRONOUS
CLOCK/CRYSTAL
16- OR 18-BIT 6
DIGITAL DATA
INPUT
AD1859
SERIAL
DATA
INTERFACE
VARIABLE RATE
INTERPOLATION
VARIABLE RATE
INTERPOLATION
POWER
DOWN/RESET
SERIAL
CONTROL
INTERFACE
VOLTAGE
REFERENCE
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MULTIBIT
∑∆ MODULATOR
DAC
ANALOG
FILTER
MUTE
DE-EMPHASIS
DPLL/CLOCK
MANAGER
ATTEN/
MUTE
ATTEN/
MUTE
OUTPUT
BUFFER
OUTPUT
BUFFER
2
ANALOG
SUPPLY
DE-EMPHASIS
SWITCH LEFT
COMMON MODE
ANALOG
OUTPUTS
DE-EMPHASIS
SWITCH RIGHT
*SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703



Analog Devices Semiconductor Electronic Components Datasheet

AD1859 Datasheet

Stereo/ Single-Supply 18-Bit Integrated DAC

No Preview Available !

AD1859 pdf
AD1859–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD)
Ambient Temperature
+5.0
25
V
°C
Input Clock (FMCLK)
Input Signal
27.1656 MHz
1001.2938 Hz
–0.5 dB Full Scale
Input Sample Rate
44.1 kHz
Measurement Bandwidth
10 Hz to 20 kHz
Input Data Word Width
18 Bits
Load Capacitance
100 pF
Input Voltage HI (VIH)
Input Voltage LO (VIL)
2.4 V
0.8 V
NOTES
I2S-Justified Mode (Ref. Figure 3).
Device Under Test (DUT) is bypassed, decoupled and dc-coupled as shown in Figure 17 (no de-emphasis circuit).
Performance of the right and left channels are identical (exclusive of “Interchannel Gain Mismatch” and “Interchannel Phase Deviation” specifications).
Attenuation setting is 0 dB.
Values in bold typeface are tested; all others are guaranteed, not tested.
ANALOG PERFORMANCE
Resolution
Dynamic Range (20 to 20 kHz, –60 dB Input)
(No A-Weight Filter)
(With A-Weight Filter)
Total Harmonic Distortion + Noise
Analog Outputs
Single-Ended Output Range (± Full Scale)
Output Impedance at Each Output Pin
Output Capacitance at Each Output Pin
External Load Impedance (THD +N –84 dB)
Out-of-Band Energy (0.5 × FS to 100 kHz)
CMOUT
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Attenuator Step Size
Attenuator Range Span
Mute Attenuation
De-Emphasis Switch (EMPL, EMPR) DC Resistance
Min
85.7
88
2.8
750
2.05
101
0.6
–61.5
–70
3
Typ
18
91
94
–88
0.004
3.0
17
2K
2.25
±1
0.01
140
± 0.1
1.0
–62.5
–74.2
10
Max
–84
0.0063
3.2
24
20
–72.5
2.45
؎5
0.225
270
1.4
–63.5
50
Units
Bits
dB
dB
dB
%
V p-p
pF
dB
V
%
dB
ppm/°C
dB
Degrees
dB
dB
dB
DIGITAL INPUTS
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
Min
Typ
Max
Units
2.4
1
1
V
0.8 V
6 µA
6 µA
20 pF
–2– REV. A



Analog Devices Semiconductor Electronic Components Datasheet

AD1859 Datasheet

Stereo/ Single-Supply 18-Bit Integrated DAC

No Preview Available !

AD1859 pdf
DIGITAL TIMING (Guaranteed over –40°C to +105°C, AVDD = DVDD = +5.0 V ± 10%)
Min Typ
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tCCH
tCCL
tCCP
tCSU
tCHD
tCLD
tCLL
tCLH
tPDRP
tMCP
FMC
tMCH
tMCL
BCLK HI Pulse Width
BCLK LO Pulse Width
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Style Mode Only)
SDATA Setup
SDATA Hold
CCLK HI Pulse Width
CCLK LO Pulse Width
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Delay
CLATCH LO Pulse Width
CLATCH HI Pulse Width
PD/RST LO Pulse Width
MCLK Period
MCLK Frequency (1/tMCP)
MCLK HI Pulse Width
MCLK LO Pulse Width
25
25
50
5
0
0
5
15
15
30
0
5
15
5
10
4 MCLK Periods
(≈150 ns @ 27 MHz)
30 37
17 27
15
15
POWER
Supplies
Voltage, Analog and Digital
Analog Current
Analog Current—Power Down
Digital Current
Digital Current—Power Down
Dissipation
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Down—Both Supplies
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Min Typ
4.5 5
29.5 36
0.5
23.5 30
6
265
147.5
117.5
30
55
52
TEMPERATURE RANGE
Specifications Guaranteed
Functionality Guaranteed
Storage
Min Typ
25
–40
–55
PACKAGE CHARACTERISTICS
SOIC θJA (Thermal Resistance [Junction-to-Ambient])
SOIC θJC (Thermal Resistance [Junction-to-Case])
SSOP θJA (Thermal Resistance [Junction-to-Ambient])
SSOP θJC (Thermal Resistance [Junction-to-Case])
Typ
120.67
13.29
190.87
15.52
AD1859
Max
60
33
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
Max
5.5
mA
15
mA
9.5
330
180
150
48
Units
V
µA
mA
mW
mW
mW
mW
dB
dB
Max
+105
+125
Units
°C
°C
°C
Units
°C/W
°C/W
°C/W
°C/W
REV. A
–3–




Part Number AD1859
Description Stereo/ Single-Supply 18-Bit Integrated DAC
Maker Analog Devices
Total Page 16 Pages
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