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Analog Devices Semiconductor Electronic Components Datasheet

AD14060L Datasheet

Quad-SHARC DSP Multiprocessor Family

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AD14060L pdf
PERFORMANCE FEATURES
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
25 Mil (0.65 mm) lead pitch
29 grams (typical)
θJC = 0.36°C/W
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
FUNCTIONAL BLOCK DIAGRAM
CPA
SPORT 1
TDI SHARC_A
(ID2–0 = 1)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
SHARC_B
(ID2–0 = 2)
CPA
SPORT 1
SSHWA,RACCKB, USBST(SA, DHDBRR3, 1H–B0G, D, RAETDAY4,7, –B0R,6M–1S,3R-0P,BRAD,,DWMRA,RP1A.2G,ED,MAADGR1C.L2K) ,
SHARC_D
CPA
(ID2–0 = 4)
SPORT 1
TDO
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SHARC_C
(ID2–0 = 3)
CPA
SPORT 1
AD14060/AD14060L
Figure 1.
00667-001
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.



Analog Devices Semiconductor Electronic Components Datasheet

AD14060L Datasheet

Quad-SHARC DSP Multiprocessor Family

No Preview Available !

AD14060L pdf
AD14060/AD14060L
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics (3.3 V, 5 V Supply)............................ 3
Explanation of Test Levels........................................................... 4
Timing Specifications....................................................................... 5
Memory Read—Bus Master........................................................ 8
Memory Write—Bus Master ....................................................... 9
Synchronous Read/Write—Bus Master................................... 10
Synchronous Read/Write—Bus Slave ...................................... 12
Multiprocessor Bus Request and Host Bus Request .............. 13
Asynchronous Read/Write—Host to AD14060/AD14060L. 15
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS ..... 17
DMA Handshake........................................................................ 18
Absolute Maximum Ratings.......................................................... 27
ESD Caution................................................................................ 27
Pin Configuration and Function Descriptions........................... 28
Pin Function Descriptions ........................................................ 30
Detailed Description ...................................................................... 34
Architectural Features................................................................ 34
Shared Memory Multiprocessing ............................................. 34
Off-Module Memory and Peripherals Interface .................... 36
REVISION HISTORY
12/04—Rev. A to Rev. B
Format Updated..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Development Tools Section ...................................... 40
Changes to Target Board for Emulator Probe Section .............. 40
Changes to Figure 27...................................................................... 42
Updated Outline Dimensions ....................................................... 48
Changes to Ordering Guide .......................................................... 48
10/97—Rev. 0 to Rev. A
4/97—Revision 0: Initial Version
Link Port I/O............................................................................... 38
Serial Ports .................................................................................. 38
Program Booting ........................................................................ 38
Host Processor Interface ........................................................... 39
Direct Memory Access (DMA) Controller ............................. 39
Applications..................................................................................... 40
Development Tools .................................................................... 40
Quad-SHARC Development Board......................................... 40
Other Package Details................................................................ 40
Target Board Connector for Emulator Probe......................... 40
Output Drive Currents .............................................................. 42
Power Dissipation ...................................................................... 42
Test Conditions........................................................................... 43
Assembly Recommendations.................................................... 45
PCB Layout Guidelines.............................................................. 46
Mechanical Characteristics ....................................................... 47
Additional Information ............................................................. 47
Outline Dimensions ....................................................................... 48
Ordering Guide .......................................................................... 48
Rev. B | Page 2 of 48



Analog Devices Semiconductor Electronic Components Datasheet

AD14060L Datasheet

Quad-SHARC DSP Multiprocessor Family

No Preview Available !

AD14060L pdf
AD14060/AD14060L
SPECIFICATIONS
Table 1. Recommended Operating Conditions
Parameter
VDD Supply Voltage (5 V)
Supply Voltage (3.3 V)
TCASE Case Operating Temperature
B Grade
Min Max
4.75 5.25
3.15 3.6
−40 +100
K Grade
Min Max
4.75 5.25
3.15 3.6
0 +85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Table 2.
Parameter
Case Test
Temp Level Test Condition
VIH1 High Level Input Voltage1
VIH2 High Level Input Voltage2
VIL Low Level Input Voltage1, 2
Full I
Full I
Full I
@ VDD = max
@ VDD = max
@ VDD = min
VOH High Level Output Voltage3, 4
VOL Low Level Output Voltage3, 4
Full I
Full I
@ VDD = min, IOH = −2.0 mA4
@ VDD = min, IOL = 4.0 mA4
IIH High Level Input Current5, 6, 7
IIL Low Level Input Current5
Full I
Full I
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
IILP Low Level Input Current6
Full I
@ VDD = max, VIN = 0 V
IILPX4 Low Level Input Current7
Full I
@ VDD = max, VIN = 0 V
IOZH Three-State Leakage Current8, 9, 10, 11 Full I
IOZL Three-State Leakage Current8, 12
Full I
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
IOZHP Three-State Leakage Current12
Full I
@ VDD = max, VIN = VDD max
IOZLC
IOZLA
IOZLAR
Three-State Leakage Current13
Three-State Leakage Current14
Three-State Leakage Current10
Full I
Full I
Full I
@ VDD = max, VIN = 0 V
@ VDD = max,
VIN = 1.5 V (5 V), 2 V (3.3 V)
@ VDD = max, VIN = 0 V
IOZLS Three-State Leakage Current9
Full I
@ VDD = max, VIN = 0 V
IOZLSX4 Three-State Leakage Current11
Full I
@ VDD = max, VIN = 0 V
IDDIN
IDDIDLE
CIN
Supply Current (Internal)15
Supply Current (Idle)16
Input Capacitance17, 18
Full IV
Full I
25°C V
tCK = 25 ns, VDD = max
VDD = max
5V
Min Typ Max
3.3 V
Min Typ Max
Unit
2.0 VDD + 0.5 2.0 VDD + 0.5 V
2.2 VDD + 0.5 2.2 VDD + 0.5 V
0.8 0.8 V
4.1 2.4 V
0.4 0.4 V
10 10 µA
10 10 µA
150 150 µA
600 600 µA
10 10 µA
10 10 µA
350 350 µA
1.5 1.5 mA
350 350 µA
4.2
150
600
1.4 2.92
800
15
4.2
150
600
1.0 2.2
760
15
mA
µA
µA
A
mA
pF
1 Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, STBS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2, BR6-1, RPBA, CPAy, TFS0,
TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS, TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0,
RCLKy1.
2 Applies to input pins: CLKIN, RESET, TRST.
3 Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG, REDY, DMAG1, DMAG2,
BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, BMSA, BMSBCD, TDO, EMU.
4 See the Output Drive Currents section for typical drive current capabilities.
5 Applies to input pins: STBS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6 Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7 Applies to bused input pins with internal pull-ups: TRST, TMS.
8 Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2, BMSA, BMSBCD, TDO,
EMU. (Note that ACK is pulled up internally with 2 kduring reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is not requesting bus
mastership. HBG and EMU are not tested for leakage current.)
9 Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kduring reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11 Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
12 Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
13 Applies to CPAy pin.
14 Applies to ACK pin, when the keeper latch is enabled.
15 Applies to VDD pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each
internal memory block, and one DMA transfer is occurring from/to internal memory at tCK = 25 ns.
16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17 Applies to all signal pins.
18 Guaranteed, but not tested.
Rev. B | Page 3 of 48




Part Number AD14060L
Description Quad-SHARC DSP Multiprocessor Family
Maker Analog Devices
Total Page 30 Pages
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