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Analog Devices Semiconductor Electronic Components Datasheet

AD1317 Datasheet

Ultrahigh Speed Window Comparator with Latch

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AD1317 pdf
a
FEATURES
Full Window Comparator
2.0 pF max Input Capacitance
9 V max Differential Input Voltage
2.5 ns Propagation Delays
Low Dispersion
Low Input Bias Current
Independent Latch Function
Input Inhibit Mode
80 dB CMRR
APPLICATIONS
High Speed Pin Electronic Receiver
High Speed Triggers
Threshold Detectors
Peak Detectors
Ultrahigh Speed
Window Comparator with Latch
AD1317
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD1317 is an ultrahigh speed window comparator with a
latch. It uses a high speed monolithic process to provide high dc
accuracy without sacrificing input voltage range. The AD1317
guarantees a 2.8 ns maximum propagation delay.
On-chip connection of the common input eliminates the contri-
butions of a second bonding pad and package pin to the input
capacitance, resulting in a maximum input capacitance of 2 pF.
The dispersion, or variation in propagation delay with input
overdrive levels and slew rates, is typically 350 ps for 5 V signals
and 200 ps for 1 V inputs.
The AD1317 employs a high precision differential input stage
with a common-mode range of 9 V. Its complementary digital
outputs are ECL compatible. The output stage is capable of
driving a 50 line terminated to –2 V. The AD1317 also pro-
vides a latch function, allowing operation in a sample-hold
mode. The latch inputs can also be used to generate hysteresis.
The comparator input can be switched into a high impedance
state through the inhibit mode feature, electrically removing the
comparator from the circuit. The bias current in inhibit mode is
typically 50 pA.
The AD1317 is available in a small 16-lead, hermetically sealed
“gull-wing” surface mount package and operates over the com-
mercial temperature range, 0°C to +70°C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997


Analog Devices Semiconductor Electronic Components Datasheet

AD1317 Datasheet

Ultrahigh Speed Window Comparator with Latch

No Preview Available !

AD1317 pdf
AD1317–SPECIFICATIONS (All specifications at +25؇C, free air. Outputs terminated into 50 to –2 V,
with + VS = +10 V, –VS = 5.2 V unless otherwise noted)
Parameter
Symbol
AD1317KZ
Min Typ Max
Units Comments
DC INPUT CHARACTERISTICS
Offset Voltage
Offset Drift
VINA/B Bias Currents
Active
Inhibit
VINA, VINB Bias Currents
Active
Inhibit
VINA/B Resistance
VINA, VINB Resistance
Capacitance VINA/B, VINA, VINB
Voltage Range
Differential Voltage
Common-Mode Rejection Ratio
VOS
dVOS/dT
Ibca
Ibci
Ibsa
Ibsi
Rinc
Rins
CIN
VCM
VDIFF
CMRR
–10
–2
70
10 mV CMV = 0 V
20 µV/°C
–2 V to +7 V
10 33
µA
50 pA
–2 V to +7 V
5 16.5 µA
50 pA
4 M
8 M
1.5 2.0
pF
7 Volts See Note 5
9 Volts
80 dB –2 V to +7 V
LATCH ENABLE INPUTS
Input Voltage, Any Input
–2.0
Differential Voltage
0.4
Logic “1” Current
Logic “0” Current
Capacitance
IIH
IIL –200
5.0 Volts
4 Volts
10 µA
µA
4 pF
INPUT ENABLE CURRENTS
Input Voltage, Any Input
Differential Voltage
Logic “1” Current
Logic “0” Current
Capacitance
IIH
IIL
–2.0
0.4
–200
5.0 Volts
4 Volts
20 µA
µA
4 pF
DIGITAL OUTPUTS
Logic “l” Voltage
Logic “0” Voltage
SWITCHING PERFORMANCE
Propagation Delays
Input to Output
Latch Enable to Output
Active to Inhibit
Inhibit to Active
Propagation Delay T.C.
Dispersion
5 V Signal
All Edges
Rising Edge
Falling Edge
1 V Signal
All Edges
Rising Edge
Falling Edge
VOH
VOL
tPDR, tPDF
tLO
tIN
tIE
–0.98
Volts
–1.50 Volts
See Figure 3
1.8 2.8
2.0 2.5
2.5
15
5
450 600
350
350
250 400
200
200
ns
ns
ns
ns
ps/°C
ps
ps
ps
ps
ps
ps
See Note 1
See Note 1
See Note 2
See Note 3
See Note 4
See Figure 1
See Figure 2
LATCH TIMING
Input Pulse Width
Setup Time
Hold Time
POWER SUPPLIES
–VS to +VS Range
Positive Supply
Negative Supply
Positive Supply Current
Negative Supply Current
PSRR
tPW 2.5 1.0
tS 1.5 0.4
tH 0
ns
ns
ns
15.2 15.6
See Note 5
+VS 8.0 10.0 11.0 Volts
–VS –7.2 –5.2 –4.2 Volts
I+
50 70
mA
I–
–100
–70
mA
65 75
dB Measured at ± 2.5% of +VS and –VS
NOTES
1Propagation Delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing.
2Propagation Delay is measured from the input crossing of IE and IE to when the input bias currents drop to 10% of their nominal value.
3Propagation Delay is measured from the input crossing of IE and IE to when the input bias currents rise to 90% of their nominal value.
4Dispersion is measured with input slew rates of 0.5 V/ns and 2.5 V/ns for 5 V swings, 0.5 V/ns and 1 V/ns for 1 V swings.
5The comparator input voltage range is specified for –2 V to +7 V for typical power supply values of -5.2 V and +10.0 V but can be offset for different input ranges such as –1 V to
+8 V with power supplies of –4.2 V and +11 V, as long as the required headroom of 3 V is maintained between both VH and +VS and VL and +VS.
Specifications subject to change without notice.
–2– REV. A


Part Number AD1317
Description Ultrahigh Speed Window Comparator with Latch
Maker Analog Devices
Total Page 12 Pages
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