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• Self-timed design allows flexibility in clock duty cycle
while maintaining fast cycle time
• 256 x 8 instantiation block
• Always active outputs
• Low standby power when the clock is stopped
• Separate input and output ports with full parallel access
• Altera Flex10 equivalent functionality
• Precharged design for faster operation with lower power
FIGURE 1: LOGIC SYMBOL
RASJ810: High Speed Low-Power Single Port
This 256x8 SRAM block is built into AMI's base arrays.
When your application requires static RAM memory, use
these RAMs. The self timed feature of this RAM allows
flexibility in the clock duty cycle while maintaining fast
cycle times. All timing is relative to the risting edge of the
clock input (CLK). When CLK rises, all inputs are latched
and the READ or WRITE operation occurs. The RAM will
stay in the READ mode and not start precharging until the
READ operations is complete, even if CLK falls. The
outputs become valid a short time after the rising edge of
CLK and stay valid unil the next rising edge of CLK. All of
the inputs including CLK can be held stable indefinately
with no loss of memory as long as power is supplied to the
RAM. See figure 2 for a block diagram of the RAM.
To obtain additional data or an EDA model contact your
sales representative or the factory.
Note: A0 is the LSB.