| Part Number | 74S112 |
| Manufacturer | Fairchild Semiconductor |
| Title | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Description | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-... |
| Features |
e Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X ↓ ↓ ↓ ↓ H J X X X L H L H X K X X X L L H H X Q0 H L H* Q0 H L Toggle Q0 Outputs Q Q L H H* Q0 L H
H = HIGH Logic ...
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| Datasheet |
 74S112 Datasheet 42.41KB |
