| Part Number | M13S128324A |
| Manufacturer | ESMT |
| Title | Double Data Rate SDRAM |
| Description | Pin Name Function Pin Name Function A0~A11, BA0,BA1 Address inputs - Row address A0~A11 - Column address A0~A7 A8/AP : AUTO Precharge BA0, B... |
| Features |
Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 2.5, 3 ... |
| Datasheet |
 M13S128324A Datasheet 1.72MB |
