| Description | The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DR... |
| Features |
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0(A13) and BA1(A12) • Byte control (×16) by LDQM and UDQM • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4... |
| Datasheet |
 D45128841G5 Datasheet - 855.93KB |
