| Part Number | QL2007 |
| Manufacturer | ETC |
| Title | pASIC 2 FPGA Combining Speed |
| Description | Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test... |
| Features |
-3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram
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| Datasheet |
 QL2007 Datasheet 331.88KB |
